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參數(shù)資料
| 型號： | ADV212BBCZRL-150 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | JPEG 2000 Video Codec |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA144 |
| 封裝： | 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144 |
| 文件頁數(shù)： | 7/44頁 |
| 文件大?。?/td> | 374K |
| 代理商： | ADV212BBCZRL-150 |
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ADV212
NORMAL HOST MODE—READ OPERATION
Rev. 0 | Page 7 of 44
Table 5.
Parameter
RD to ACK, Direct Registers and FIFO Accesses
Mnemonic
t
ACK
(direct)
1
t
ACK
(indirect)
1
t
DRD
(direct)
t
DRD
(indirect)
t
HZRD
t
SC
t
SA
t
HC
t
HA
t
RH
t
RL
t
RCYC
Min
5
Typ
Max
1.5 × JCLK + 7.0
Unit
ns
RD to ACK, Indirect Registers
Read Access Time, Direct Registers
Read Access Time, Indirect Registers
Data Hold
CS to RD Setup
Address Setup
CS Hold
Address Hold
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
1
Timing relationship between ACK falling transition and HDATA valid is not guaranteed. HDATA valid hold time is guaranteed with respect to RD rising transition. A
minimum of three JCLK cycles is recommended between ACK assert and RD deassert.
2
For a definition of JCLK, see Figure 32.
10.5 × JCLK
15.5 × JCLK + 7.0
ns
5
10.5 × JCLK
2
0
2
0
2
2.5 JCLK
2
2.5 JCLK
5.0 JCLK
1.5 × JCLK + 7.0
15.5 × JCLK + 7.0
8.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADDR
t
SA
t
SC
t
HA
t
HC
t
RL
t
ACK
t
DRD
t
HZRD
t
RH
t
RCYC
HDATA
CS
RD
ACK
VALID
0
Figure 4. Normal Host Mode—Read Operation
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| ADV212-HD-EB | 功能描述:BOARD EVALUATION FOR ADV212-HD RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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| ADV226KBCZ | 制造商:Analog Devices 功能描述: |
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