參數(shù)資料
型號： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁數(shù)： 12/44頁
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Rev. 0 | Page 12 of 44
Table 8.
Parameter
DREQ Pulse Width
1
WE to DREQ Deassert (DR × PULS = 0)
Mnemonic
DREQ
PULSE
t
DREQRTN
t
DACKSU
t
SU
t
HD
WE
LO
WE
HI
t
DREQWAIT
t
WE_DACK
Min
1 JCLK
2
2.5 JCLK
Typ
Max
15 JCLK
3.5 × JCLK + 7.5
Unit
ns
ns
DACK to WE Setup
0
ns
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
WEDeassert to Next DREQ
2.5
2
1.5 JCLK
1.5 JCLK
2.5 JCLK
4.5 × JCLK + 9.0
ns
ns
ns
ns
ns
WE Deassert to DACK Deassert
0
ns
1
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2
For a definition of JCLK, see Figure 32.
DREQ
DACK
WE
HDATA
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
DREQ
PULSE
t
WE_DACK
0
Figure 13. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
t
DREQRTN
DREQ
DACK
WE
WE
HI
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
HDATA
t
WE_DACK
0
Figure 14. Burst Write Cycle for DREQ/DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
t
DREQRTN
DREQ
DACK
WEFB
HDATA
WE
LO
t
DACKSU
t
HD
t
SU
0
1
13
14
15
t
DREQWAIT
WE
HI
t
WE_DACK
0
Figure 15. Burst Write Cycle for Fly-By DMA Mode
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