參數(shù)資料
型號： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁數(shù)： 35/44頁
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the host.
Rev. 0 | Page 35 of 44
In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
DATA[31:0]
ADDR[3:0]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
CS
RD
WR
ACK
IRQ
CS
RD
WR
ACK
IRQ
DREQ
DACK
DREQ
DACK
DREQ
DACK
FIELD
VSYNC
HSYNC
G I/O
SCOMM[5]
VCLK
1080i
VIDEO OUT
MCLK
VDATA[11:2]
32-BIT HOST CPU
ADV7321A
10-BIT SD/HD
VIDEO
ENCODER
ADV212_1_MASTER
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
FIELD
VSYNC
HSYNC
DREQ
DACK
VCLK
MCLK
VDATA[11:2]
ADV212_2_SLAVE
CLKIN
Y[9:0]
C[9:0]
CbCr
CbCr
Y
Y
74.25MHz
OSC
0
Figure 34. Decode—Multichip Master/Slave Application
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