參數(shù)資料
型號： ADV212BBCZRL-150
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： JPEG 2000 Video Codec
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA144
封裝： 13 X 13 MM, LEAD FREE, MO-192AAD-1, CSPBGA-144
文件頁數(shù)： 10/44頁
文件大?。?/td> 374K
代理商： ADV212BBCZRL-150
ADV212
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Rev. 0 | Page 10 of 44
Table 7.
Parameter
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
Mnemonic
DREQ
PULSE
t
DREQ
t
RDSU
t
RD
t
HD
DACK
LO
DACK
HI
t
RDHD
RDFSRQ
t
DREQRTN
Min
1 JCLK
1
2.5 JCLK
Typ
Max
15 JCLK
3.5 × JCLK + 9.0
Unit
ns
ns
RD to DACK Setup
0
ns
DACK to Data Valid
Data Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold after DACK Deassert
2.5
1.5
2 JCLK
2 JCLK
0
11
ns
ns
ns
ns
ns
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
1.5 JCLK
2.5 JCLK
2.5 × JCLK + 9.0
3.5 × JCLK + 9.0
ns
ns
1
For a definition of JCLK, see Figure 32.
RD
DACK
DREQ
HDATA
0
1
2
t
RD
t
HD
DREQ
PULSE
t
DREQ
t
RDSU
t
RDHD
DACK
HI
DACK
LO
0
Figure 9. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Not Programmed to a Value of 0000)
RD
DACK
DREQ
HDATA
0
1
2
t
RD
t
HD
t
DREQRTN
t
RDSU
t
RDHD
DACK
HI
DACK
LO
0
Figure 10. Single Read for DREQ/DACK DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
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