AV
參數(shù)資料
型號： ADUC847BSZ8-5
廠商： Analog Devices Inc
文件頁數(shù)： 96/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/24BIT ADC 52MQFP
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 88 of 108
as op amps and voltage reference) can be powered from the
AVDD supply line as well.
DVDD
AGND
AVDD
DGND
DIGITAL SUPPLY
–
+
BEAD
1.6
0.1
F
0.1
F
10
F
10
F
ADuC845/
ADuC847/
ADuC848
04741-062
6
5
4
22
36
51
50
38
37
23
Figure 65. External Single-Supply Connections
(56-Lead LFCSP Pin Numbering)
Notice that in both Figure 64 and Figure 65 a large value (10 F)
reservoir capacitor sits on DVDD and a separate 10 F capacitor
sits on AVDD. Also, local decoupling capacitors (0.1 F) are
located at each VDD pin of the chip. As per standard design
practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are closer than the 10 F capacitors
to each VDD pin with lead lengths as short as possible. Connect
the ground terminal of each of these capacitors directly to the
underlying ground plane. Finally, note that, at all times, the
analog and digital ground pins on the part must be referenced
to the same system ground reference point. It is recommended
that the LFCSP paddle be soldered to ensure mechanical
stability but be floated with respect to system VDDs or grounds.
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC845/ADuC847/ADuC848.
3 V Part
For DVDD below 2.63 V, the internal POR holds the part in reset.
As DVDD rises above 2.63 V, an internal timer times out for
typically 128 ms before the part is released from reset. The user
must ensure that the power supply has at least reached a stable
2.7 V minimum level by this time. Likewise on power-down,
the internal POR holds the part in reset until the power supply
drops below 1 V. Figure 66 illustrates the operation of the
internal POR.
128ms TYP
1.0V TYP
128ms TYP
2.63V TYP
1.0V TYP
INTERNAL
CORE RESET
DVDD
04741-063
Figure 66. 3 V Part POR operation
5 V Part
For DVDD below 4.5 V, the internal POR holds the part in reset.
As DVDD rises above 4.5 V, an internal timer times out for
approximately 128 ms before the part is released from reset. The
user must ensure that the power supply has reached a stable
4.75 V minimum level by this time. Likewise on power-down,
the internal POR holds the part in reset until the power supply
drops below 1 V. Figure 67 illustrates this operation.
128ms TYP
1.0V TYP
128ms TYP
4.5V TYP
1.0V TYP
INTERNAL
CORE RESET
DVDD
04741-087
Figure 67. 5 V Part POR Operation
POWER CONSUMPTION
The DVDD power supply current consumption is specified in
normal and power-down modes. The AVDD power supply
current is specified with the analog peripherals disabled. The
normal mode power consumption represents the current drawn
from DVDD by the digital core. The other on-chip peripherals
(such as the watchdog timer and power supply monitor)
consume negligible current and are therefore included with the
normal operating current. The user must add any currents
sourced by the parallel and serial I/O pins, and those sourced by
the DAC to determine the total current needed at the ADuC845/
ADuC847/ADuC848 DVDD and AVDD supply pins. Also, current
drawn from the DVDD supply increases by approximately 5 mA
during Flash/EE erase and program cycles.
POWER-SAVING MODES
Setting the power-down mode bit, PCON.1, in the PCON SFR
described in Table 6, allows the chip to be switched from
normal mode into full power-down mode.
In power-down mode, both the PLL and the clock to the core
are stopped. The on-chip oscillator can be halted or can
continue to oscillate, depending on the state of the oscillator
power-down bit (OSC_PD) in the PLLCON SFR. The TIC,
driven directly from the oscillator, can also be enabled during
power-down. However, all other on-chip peripherals are shut
down. Port pins retain their logic levels in this mode, but the
DAC output goes to a high impedance state (three-state) while
ALE and PSEN outputs are held low. There are five ways to
terminate power-down mode:
Asserting the RESET Pin
Returns to normal mode. All registers are set to their reset
default value and program execution starts at the reset
vector once the RESET pin is de-asserted.
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