參數(shù)資料
型號： ADUC847BSZ8-5
廠商： Analog Devices Inc
文件頁數(shù)： 44/108頁
文件大?。?/td> 0K
描述： IC MCU FLASH W/24BIT ADC 52MQFP
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 8KB（8K x 8）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 40 of 108
ADCSTAT (ADC STATUS REGISTER)
This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions
including REFIN± reference detect and conversion overflow/underflow flags.
SFR Address:
D8H
Power-On Default:
00H
Bit Addressable:
Yes
Table 23. ADCSTAT SFR Bit Designation
Bit No.
Name
Description
7
RDY0
Ready Bit for the Primary ADC.
Set by hardware on completion of conversion or calibration.
Cleared directly by the user, or indirectly by a write to the mode bits, to start calibration. The primary ADC is
inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared.
6
RDY1
Ready Bit for Auxiliary (ADuC845 only) ADC.
Same definition as RDY0 referred to the auxiliary ADC. Valid on the ADuC845 only.
5
CAL
Calibration Status Bit.
Set by hardware on completion of calibration.
Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration.
Note that calibration with the temperature sensor selected (auxiliary ADC on the ADuC845 only) fails to complete.
4
NOXREF
No External Reference Bit (only active if primary or auxiliary (ADuC845 only) ADC is active).
Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold.
When set, conversion results are clamped to all 1s. Only detects invalid REFIN±, does not check REFIN2±.
Cleared to indicate valid VREF.
3
ERR0
Primary ADC Error Bit.
Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all 0s or
all 1s. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written.
Cleared by a write to the mode bits to initiate a conversion or calibration.
2
ERR1
Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. Valid on the ADuC845 only.
1
–––
Not Implemented. Write Don’t Care.
0
–––
Not Implemented. Write Don’t Care.
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