參數(shù)資料
型號(hào)： ADUC847BSZ8-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH W/24BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 30 of 108
Signal Chain Overview with Chop Disabled (CHOP = 1)
With CHOP = 1, chop is disabled and the available output rates
vary from 16.06 Hz to 1.365 kHz. The range of applicable SF
words is from 3 to 255. When switching between channels with
chop disabled, the channel throughput rate is higher than when
chop is enabled. The drawback with chop disabled is that the
drift performance is degraded and offset calibration is required
following a gain range change or significant temperature
change. A block diagram of the ADC input channel with chop
disabled is shown in Figure 15.
The signal chain includes a multiplex or buffer, PGA, Σ-Δ
modulator, and digital filter. The modulator bit stream is
applied to a Sinc3 filter. Programming the Sinc3 decimation
factor is restricted to an 8-bit register SF; the actual decimation
factor is the register value times 8. The decimated output rate
from the Sinc3 filter (and the ADC conversion rate) is therefore
MOD
ADC
f
SF
f
×
=
8
1
where:
fADC is the ADC conversion rate.
SF is the decimal equivalent of the word loaded to the filter
register, valid range is from 3 to 255.
fMOD is the modulator sampling rate of 32.768 kHz.
The settling time to a step input is governed by the digital filter.
A synchronized step change requires a settling time of three
times the programmed update rate; a channel change can be
treated as a synchronized step change. This is one conversion
longer than the case for chop enabled. However, because the
ADC throughput is three times faster with chop disabled than it
is with chop enabled, the actual time to a settled ADC output is
significantly less also. This means that following a synchronized
step change, the ADC requires three conversions (note: data is
not output following a synchronized ADC change until data has
settled) before the result accurately reflects the new input
voltage.
ADC
SETTLE
t
f
t
×
=
3
An unsynchronized step change requires four conversions to
accurately reflect the new analog input at its output. Note that
with an unsynchronized change the ADC continues to output
data and so the user must take unsettled outputs into account.
Again, this is one conversion longer than with chop enabled, but
because the ADC throughput with chop disabled is faster than
with chop enabled, the actual time taken to obtain a settled
ADC output is less.
The allowable range for SF is 3 to 255 with a default of 69 (45H).
The corresponding conversion rates, rms, and peak-to-peak
noise performances are shown in Table 14, Table 15, Table 16,
and Table 17. Note that the conversion time increases by 0.244 ms
for each increment in SF.
SINC3 FILTER
PGA
8
× SF
S-D
MOD
FADC
DIGITAL
OUTPUT
ANALOG
INPUT
MUX
BUF
FMOD
FIN
04741-015
Figure 15. Block Diagram of ADC Input Channel with Chop Disabled
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