- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11199 > ADUC847BSZ8-5 (Analog Devices Inc)IC MCU FLASH W/24BIT ADC 52MQFP PDF資料下載
參數(shù)資料
| 型號： | ADUC847BSZ8-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/108頁 |
| 文件大小： | 0K |
| 描述： | IC MCU FLASH W/24BIT ADC 52MQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x24b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 配用： | EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁
ADuC845/ADuC847/ADuC848
Data Sheet
Rev. C | Page 22 of 108
Mnemonic
Description
Bytes
Cycles1
SJMP rel
Short jump (relative address)
2
3
JC rel
Jump on carry = 1
2
3
JNC rel
Jump on carry = 0
2
3
JZ rel
Jump on accumulator = 0
2
3
JNZ rel
Jump on accumulator ! = 0
2
3
DJNZ Rn,rel
Decrement register, JNZ relative
2
3
LJMP
Long jump unconditional
3
4
LCALL3 addr16
Long jump to subroutine
3
4
JB bit,rel
Jump on direct bit = 1
3
4
JNB bit,rel
Jump on direct bit = 0
3
4
JBC bit,rel
Jump on direct bit = 1 and clear
3
4
CJNE A,dir,rel
Compare A, direct JNE relative
3
4
CJNE A,#data,rel
Compare A, immediate JNE relative
3
4
CJNE Rn,#data,rel
Compare register, immediate JNE relative
3
4
CJNE @Ri,#data,rel
Compare indirect, immediate JNE relative
3
4
DJNZ dir,rel
Decrement direct byte, JNZ relative
3
4
Miscellaneous
NOP
No operation
1
One cycle is one clock.
2
MOVX instructions are four cycles when they have 0 wait state. Cycles of MOVX instructions are 4 + n cycles when they have n wait states as programmed via EWAIT.
3
LCALL instructions are three cycles when the LCALL instruction comes from an interrupt.
MEMORY ORGANIZATION
The ADuC845, ADuC847, and ADuC848 contain four memory
blocks:
62 kbytes/32 kbytes/8 kbytes of on-chip Flash/EE program
memory
4 kbytes of on-chip Flash/EE data memory
256 bytes of general-purpose RAM
2 kbytes of internal XRAM
Flash/EE Program Memory
The parts provide up to 62 kbytes of Flash/EE program memory
to run user code. All further references to Flash/EE program
memory assume the 62-kbyte option.
When EA is pulled high externally during a power cycle or a
hardware reset, the parts default to code execution from their
internal 62 kbytes of Flash/EE program memory. The parts do
not support the rollover from internal code space to external
code space. No external code space is available on the parts.
Permanently embedded firmware allows code to be serially
downloaded to the 62 kbytes of internal code space via the
UART serial port while the device is in-circuit. No external
hardware is required.
During run time, 56 kbytes of the 62-kbyte program memory
can be reprogrammed. This means that the code space can be
upgraded in the field by using a user-defined protocol running
on the parts, or it can be used as a data memory. For details, see
the Nonvolatile Flash/EE Memory Overview section.
Flash/EE Data Memory
The user has 4 kbytes of Flash/EE data memory available that
can be accessed indirectly by using a group of registers mapped
into the special function register (SFR) space. For details, see
General-Purpose RAM
The general-purpose RAM is divided into two separate
memories, the upper and the lower 128 bytes of RAM. The
lower 128 bytes of RAM can be accessed through direct or
indirect addressing. The upper 128 bytes of RAM can be
accessed only through indirect addressing because it shares the
same address space as the SFR space, which must be accessed
through direct addressing.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 8. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 to R7. The next 16 bytes
(128 bits), locations 20H to 2FH above the register banks, form
a block of directly addressable bit locations at Bit Addresses
00H to 7FH. The stack can be located anywhere in the internal
memory address space, and the stack depth can be expanded up
to 2048 bytes.
Reset initializes the stack pointer to location 07H. Any call or
push pre-increments the SP before loading the stack. Therefore,
loading the stack starts from location 08H, which is also the
first register (R0) of Register Bank 1. Thus, if one is going to use
more than one register bank, the stack pointer should be
initialized to an area of RAM not used for data storage.
相關PDF資料 |
PDF描述 |
|---|---|
| AT91SAM7SE512-CU-999 | IC MCU ARM7 512KB FLASH 144LFBGA |
| NLVAS4599DTT1G | IC SWITCH SPDT 6TSOP |
| ADUC843BCP62Z-5 | IC MCU FLASH 12BIT ADC 56LFCSP |
| ADUC816BSZ-REEL | IC MCU FLASH 16BIT ADC 52MQFP |
| NLVAS4599DFT2G | IC SWITCH SPDT SC88 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC848 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter Multichannel 24-/16-Bit ADCs with Embedded 62 kB Flash and Single-Cycle MCU |
| ADUC848BCP32-3 | 制造商:Analog Devices 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Trays |
| ADUC848BCP32-5 | 制造商:Analog Devices 功能描述:10 CHANNEL 16 BIT ADC + FLASH 8 BIT UP - Trays |
| ADUC848BCP62-3 | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 12.85MHZ 3.3V 56LFCSP - Bulk |
| ADUC848BCP62-5 | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 56-Pin LFCSP EP |
發(fā)布緊急采購，3分鐘左右您將得到回復。