參數(shù)資料
型號(hào)： ADUC847BSZ8-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 95/108頁(yè)
文件大?。?/td> 0K
描述： IC MCU FLASH W/24BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x24b; D/A 1x12b，2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-QFP
包裝： 托盤
配用： EVAL-ADUC847QSZ-ND - KIT DEV QUICK START FOR ADUC847
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 87 of 108
HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design
considerations that must be addressed when integrating the
ADuC845/ADuC847/ADuC848 into any hardware system.
EXTERNAL MEMORY INTERFACE
In addition to their internal program and data memories, the
parts can access up to 16 Mbytes of external data memory
(SRAM). No external program memory access is available.
To begin executing code, tie the EA (external access) pin high.
When EA is high (pulled up to VDD—see Figure 70), user
program execution starts at Address 0 in the internal 62-kbyte
Flash/EE code space. When executing from internal code space,
accesses to the program space above F7FFH (62 kbytes) are read
as NOP instructions.
Note that a second very important function of the EA pin is
described in the Single-Pin Emulation Mode section under the
Figure 62 shows a hardware configuration for accessing up to
64 kbytes of external data memory. This interface is standard to
any 8051-compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC845/
ADuC847/
ADuC848
RD
P2
ALE
P0
WE
WR
04741-059
Figure 62. External Data Memory Interface (64-kbyte Address Space)
If access to more than 64 kbytes of RAM is desired, a feature
unique to the MicroConverter allows addressing up to 16 Mbytes
of external RAM simply by adding another latch as shown in
LATCH
P2
ALE
P0
LATCH
SRAM
A8–A15
A0–A7
D0–D7
(DATA)
A16–A23
OE
RD
WE
WR
ADuC845/
ADuC847/
ADuC848
04741-060
Figure 63. External Data Memory Interface (16-Mbtye Address Space)
In either implementation, Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the data pointer (DPL)
as an address, which is latched by ALE prior to data being placed
on the bus by the parts (write operation) or the external data
memory (read operation). Port 2 (P2) provides the data pointer
page byte (DPP) to be latched by ALE, followed by the data
pointer high byte (DPH). If no latch is connected to P2, DPP is
ignored by the SRAM, and the 8051 standard of 64-kbyte external
data memory access is maintained.
The following example shows the code used to write data to
external data memory.
MOV DPP, #10h ;Set addr to 100000h
MOV DPH, #00h
MOV DPL, #00h
MOV A,
#'B' ;Write Char ‘B’ (42h)
MOVX @DPTR,A
;Move to DPP:DPH:DPL addr
POWER SUPPLIES
The parts’ operational power supply voltage range is 2.7 V to
5.25 V. Although the guaranteed data sheet specifications are
given only for power supplies within 2.7 V to 3.6 V and 4.75 V
to 5.25 V (±5% of the nominal 5 V level), the chip functions
equally well at any power supply level between 2.7 V and 5.25 V.
Separate analog and digital power supply pins (AVDD and DVDD,
respectively) allow AVDD to be kept relatively free of the noisy
digital signals often present on a system DVDD line. In this mode,
the part can also operate with split supplies, that is, using different
voltage supply levels for each supply. For example, the system
can be designed to operate with a DVDD voltage level of 3 V and
the AVDD level can be at 5 V, or vice versa, if required. A typical
split-supply configuration is shown in Figure 64.
DIGITAL SUPPLY
ANALOG SUPPLY
DVDD
AGND
AVDD
DGND
–
+
–
+
0.1
F
0.1
F
10
F
10
F
ADuC845/
ADuC847/
ADuC848
04741-061
6
5
4
22
36
51
50
38
37
23
Figure 64. External Dual-Supply Connections
(56-Lead LFCSP Pin Numbering)
As an alternative to providing two separate power supplies,
AVDD can be kept quiet by placing a small series resistor and/or
ferrite bead between it and DVDD, and then decoupling AVDD
separately to ground. An example of this configuration is shown
in Figure 65. In this configuration, other analog circuitry (such
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