參數(shù)資料
型號(hào)： ADUC841BSZ62-5
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 65/88頁(yè)
文件大小： 0K
描述： IC ADC/DAC 12BIT W/MCU 52-MQFP
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
配用： EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 68 of 88
Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high
speed baud rates are not always possible using some particular
crystals. For example, using a 12 MHz crystal, a baud rate of
115200 is not possible. To address this problem, the part has
added a dedicated baud rate timer (Timer 3) specifically for
generating highly accurate baud rates. Timer 3 can be used
instead of Timer 1 or Timer 2 for generating very accurate high
speed UART baud rates including 115200 and 230400. Timer 3
also allows a much wider range of baud rates to be obtained. In
fact, every desired bit rate from 12 bit/s to 393216 bit/s can be
generated to within an error of ±0.8%. Timer 3 also frees up the
other three timers, allowing them to be used for different
applications. A block diagram of Timer 3 is shown in Figure 74.
(1 + T3FD/64)
2
T3 RX/TX
CLOCK
CORE
CLK
T3EN
RX CLOCK
TX CLOCK
TIMER 1/TIMER 2
RX CLOCK
FRACTIONAL
DIVIDER
0
1
TIMER 1/TIMER 2
TX CLOCK
16
2DIV
03260-0-074
Figure 74. Timer 3, UART Baud Rates
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
The appropriate value to write to the DIV2-1-0 bits can be
calculated using the following formula where fCORE is defined in
PLLCON SFR. Note that the DIV value must be rounded down.
()
2
log
16
log
×
=
Rate
Baud
f
DIV
CORE
T3FD is the fractional divider ratio required to achieve the
required baud rate. The appropriate value for T3FD can be
calculated with the following formula:
64
2
3
1
×
=
Rate
Baud
f
FD
T
DIV
CORE
Note that T3FD should be rounded to the nearest integer. Once
the values for DIV and T3FD are calculated, the actual baud rate
can be calculated with the following formula:
()
64
3
2
1
+
×
=
FD
T
f
Rate
Baud
Actual
DIV
CORE
For example, to get a baud rate of 115200 while operating at
16.7 MHz, i.e., CD = 0
(
)
(
)
()
H
FD
T
DIV
09
9
64
115200
2
/
16777216
2
3
18
.
3
2
log
/
115200
16
/
16777216
log
2
=
×
=
×
=
Therefore, the actual baud rate is 114912 bit/s.
Table 33. T3CON SFR Bit Designations
Bit No.
Name
Description
7
T3BAUDEN
T3UARTBAUD Enable.
Set to enable Timer 3 to generate the baud rate. When set, PCON.7, T2CON.4, and T2CON.5 are ignored.
Cleared to let the baud rate be generated as per a standard 8052.
6
Reserved.
5
Reserved.
4
Reserved.
3
Reserved.
2
DIV2
Binary Divider Factor.
1
DIV1
DIV2
DIV1
DIV0
Bin Divider
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
DIV0
1
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