- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄12014 > ADUC841BSZ62-5 (Analog Devices Inc)IC ADC/DAC 12BIT W/MCU 52-MQFP PDF資料下載
參數(shù)資料
| 型號： | ADUC841BSZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC/DAC 12BIT W/MCU 52-MQFP |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b，D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁當(dāng)前第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 60 of 88
Timers/Counters
The ADuC841/ADuC842/ADuC843 have three 16-bit timer/
counters: Timer 0, Timer 1, and Timer 2. The timer/counter
hardware is included on-chip to relieve the processor core of the
overhead inherent in implementing timer/counter functionality
in software. Each timer/counter consists of two 8-bit registers:
THx and TLx (x = 0, 1, and 2). All three can be configured to
operate either as timers or as event counters.
In timer function, the TLx register is incremented every
machine cycle. Thus, one can think of it as counting machine
cycles. Since a machine cycle on a single-cycle core consists of
one core clock period, the maximum count rate is the core clock
frequency.
In counter function, the TLx register is incremented by a 1-to-0
transition at its corresponding external input pin: T0, T1, or T2.
When the samples show a high in one cycle and a low in the
next cycle, the count is incremented. Since it takes two machine
cycles (two core clock periods) to recognize a 1-to-0 transition,
the maximum count rate is half the core clock frequency.
There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once
before it changes, it must be held for a minimum of one full
machine cycle. User configuration and control of all timer
operating modes is achieved via three SFRs:
TMOD, TCON
Control and configuration for
Timers 0 and 1.
T2CON
Control and configuration for
Timer 2.
TMOD
Timer/Counter 0 and 1 Mode
Register
SFR Address
89H
Power-On Default
00H
Bit Addressable
No
Table 28. TMOD SFR Bit Designations
Bit No.
Name
Description
7
Gate
Timer 1 Gating Control.
Set by software to enable Timer/Counter 1 only while the INT1 pin is high and the TR1 control bit is set.
Cleared by software to enable Timer 1 whenever the TR1 control bit is set.
6
C/T
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
5
M1
Timer 1 Mode Select Bit 1 (Used with M0 Bit).
Timer 1 Mode Select Bit 0.
M1
M0
0
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it
overflows.
4
M0
1
Timer/Counter 1 Stopped.
3
Gate
Timer 0 Gating Control.
Set by software to enable Timer/Counter 0 only while the INT0 pin is high and the TR0 control bit is set.
Cleared by software to enable Timer 0 whenever the TR0 control bit is set.
2
C/T
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
1
M1
Timer 0 Mode Select Bit 1.
Timer 0 Mode Select Bit 0.
M1
M0
0
TH0 operates as an 8-bit timer/counter. TL0 serves as a 5-bit prescaler.
0
1
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler.
1
0
8-Bit Autoreload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it
overflows.
0
M0
1
TL0 is an 8-bit timer/counter controlled by the standard Timer 0 control bits.
TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VJ1825Y103JBGAT4X | CAP CER 10000PF 1KV 5% X7R 1825 |
| SCRU-01 | CONN RCPT IP68 USB A PNL MNT |
| VJ1825Y153JBGAT4X | CAP CER 0.015UF 1KV 5% X7R 1825 |
| VJ1825Y223JBGAT4X | CAP CER 0.022UF 1KV 5% X7R 1825 |
| UB-MC5ABR3-SD204-4S-TB NMP | CONN RECEPT USB MICRO AB R/A SMT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADUC841BSZ62-5 | 制造商:Analog Devices 功能描述:8-Bit Microcontroller IC |
| ADUC842 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU |
| ADUC842BCP | 制造商:AD 制造商全稱:Analog Devices 功能描述:12- Bit ADCs and DACs with Embedded Hi-Speed 62KB FLASH MCU |
| ADUC842BCP32-3 | 制造商:Rochester Electronics LLC 功能描述:8BIT CISC 62KB FLASH 16.7MHZ 3.3V 56LFCSP - Bulk 制造商:Analog Devices 功能描述: |
| ADUC842BCP32-5 | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 5V 56-Pin LFCSP EP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。