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參數(shù)資料
型號： ADUC841BSZ62-5
廠商： Analog Devices Inc
文件頁數(shù)： 44/88頁
文件大?。?/td> 0K
描述： IC ADC/DAC 12BIT W/MCU 52-MQFP
產(chǎn)品培訓模塊： Process Control
標準包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 20MHz
連通性： I²C，SPI，UART/USART
外圍設備： DMA，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 32
程序存儲器容量： 62KB（62K x 8）
程序存儲器類型： 閃存
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤
產(chǎn)品目錄頁面： 738 (CN2011-ZH PDF)
配用： EVAL-ADUC841QSZ-ND - KIT DEV FOR ADUC841 QUICK START
ADuC841/ADuC842/ADuC843
Rev. 0 | Page 49 of 88
Bit No.
Name
Description
2
I2CRS
I2C Reset Bit (Slave Mode Only).
Set by the user to reset the I2C interface.
Cleared by the user code for normal I2C operation.
1
I2CTX
I2C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
0
I2CI
I2C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
I2CADD
I2C Address Register
Function
Holds the first I2C peripheral address for the part. It may be overwritten by user code. Application Note
uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in
detail.
SFR Address
9BH
Power-On Default
55H
Bit Addressable
No
I2CADD1
I2C Address Register
Function
Holds the second I2C peripheral address for the part. It may be overwritten by user code.
SFR Address
91H
Power-On Default
7FH
Bit Addressable
No
I2CADD2
I2C Address Register
Function
Holds the third I2C peripheral address for the part. It may be overwritten by user code.
SFR Address
92H
Power-On Default
7FH
Bit Addressable
No
I2CADD3
I2C Address Register
Function
Holds the fourth I2C peripheral address for the part. It may be overwritten by user code.
SFR Address
93H
Power-On Default
7FH
Bit Addressable
No
I2CDAT
I2C Data Register
Function
Written by the user to transmit data over the I2C interface or read by user code to read data just
received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and
the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
SFR Address
9AH
Power-On Default
00H
Bit Addressable
No
The main features of the MicroConverter I2C interface are
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I2C master can communicate with multiple slave
devices. Because each slave device has a unique 7-bit
address, single master/slave relationships can exist at all
times even in a multislave environment.
Ability to respond to four separate addresses when
operating in slave mode.
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