參數資料
型號: ADUC832BCP
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述: 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝: MO-112AC-1, MQFP-52
文件頁數: 61/80頁
文件大?。?/td> 1311K
代理商: ADUC832BCP
REV. 0
ADuC832
–61–
Interrupt Priority
The Interrupt Enable registers are written by the user to enable
individual interrupt sources, while the Interrupt Priority registers
allow the user to select one of two priority levels for each interrupt.
An interrupt of a high priority may interrupt the service routine
of a low priority interrupt, and if two interrupts of different priority
occur at the same time, the higher level interrupt will be serviced
first. An interrupt cannot be interrupted by another interrupt of
the same priority level. If two interrupts of the same priority level
occur simultaneously, a polling sequence is observed as shown
in Table XXXII.
Table XXXII. Priority within an Interrupt Level
Source
Priority
Description
PSMI
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI + TI
TF2 + EXF2
TII
1 (Highest)
2
2
3
4
5
6
7
8
9 (Lowest)
11(Lowest)
Power Supply Monitor Interrupt
Watchdog Timer Interrupt
External Interrupt 0
ADC Interrupt
Timer/Counter 0 Interrupt
External Interrupt 1
Timer/Counter 1 Interrupt
SPI Interrupt/I
2
C Interrupt
Serial Interrupt
Timer/Counter 2 Interrupt
Time Interval Counter Interrupt
Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack and the corresponding interrupt vector address is loaded
into the program counter. The Interrupt Vector Addresses are
shown in Table XXXIII.
Table XXXIII. Interrupt Vector Addresses
Source
Vector Address
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ADCI
ISPI/I2CI
PSMI
TII
WDS
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH
ADuC832 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design consider-
ations that must be addressed when integrating the ADuC832
into any hardware system.
Clock Oscillator
The clock source for the ADuC832 can be generated by the
internal PLL or by an external clock input. To use the internal
PLL, connect a 32.768 kHz parallel resonant crystal between
XTAL1 and XTAL2, and connect a capacitor from each pin to
ground as shown below. This crystal allows the PLL to lock cor-
rectly to give a f
VCO
of 16.777216 MHz. If no crystal is present,
the PLL will free run, giving a f
VCO
of 16.7 MHz 20%. This is
useful if an external clock input is required. The part will power
up and the PLL will free run; the user then in software writes to
the CFG832 SFR to enable the external clock input on P3.4.
XTAL2
XTAL1
TO INTERNAL
TIMING CIRCUITS
ADuC832
Figure 55. External Parallel Resonant Crystal Connections
P3.4
TO INTERNAL
TIMING CIRCUITS
ADuC832
EXTERNAL
CLOCK
SOURCE
Figure 56. Connecting an External Clock Source
Whether using the internal PLL or an external clock source, the
ADuC832
s specified operational clock speed range is 400 kHz to
16.777216 MHz. The core itself is static, and will function all
the way down to dc. But at clock speeds slower that 400 kHz, the
ADC will no longer function correctly. Therefore, to ensure
specified operation, use a clock frequency of at least 400 kHz and
no more than 16.777216 MHz.
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