參數(shù)資料
型號: ADUC832BCP
廠商: ANALOG DEVICES INC
元件分類: 微控制器/微處理器
英文描述: MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述: 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝: MO-112AC-1, MQFP-52
文件頁數(shù): 33/80頁
文件大?。?/td> 1311K
代理商: ADUC832BCP
REV. 0
ADuC832
–33–
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 21. Details of the actual DAC
architecture can be found in U.S. Patent Number 5969657
(www.uspto.gov). Features of this architecture include inherent
guaranteed monotonicity and excellent differential linearity.
OUTPUT
BUFFER
HIGH Z
DISABLE
(FROM MCU)
DAC0
R
R
R
R
R
ADuC832
AV
DD
V
REF
Figure 21. Resistor String DAC Functional Equivalent
As illustrated in Figure 21, the reference source for each DAC
is user selectable in software. It can be either AV
DD
or V
REF.
In
0-to-AV
DD
mode, the DAC output transfer function spans from
0 V to the voltage at the AV
DD
pin. In 0-to-V
REF
mode, the DAC
output transfer function spans from 0 V to the internal V
REF
or,
if an external reference is applied, the voltage at the V
REF
pin. The
DAC output buffer amplifier features a true rail-to-rail output
stage implementation. This means that, unloaded, each output
is capable of swinging to within less than 100 mV of both AV
DD
and ground. Moreover, the DAC
s linearity specification (when
driving a 10 k
resistive load to ground) is guaranteed through
the full transfer function
except
codes 0 to 100, and, in 0-to-AV
DD
mode only, codes 3995 to 4095. Linearity degradation near
ground and V
DD
is caused by saturation of the output amplifier,
and a general representation of its effects (neglecting offset and
gain error) is illustrated in Figure 22. The dotted line in Figure 22
indicates the
ideal
transfer function, and the solid line represents
what the transfer function might look like with endpoint nonlinear-
ities due to saturation of the output amplifier. Note that Figure 22
represents a transfer function in 0-to-V
DD
mode only. In 0-to-
V
REF
mode (with V
REF
< V
DD
) the lower nonlinearity would be
similar, but the upper portion of the transfer function would
follow the
ideal
line right to the end (V
REF
in this case, not V
DD
),
showing no signs of endpoint linearity errors.
V
DD
V
DD
–50mV
V
DD
–100mV
100mV
50mV
0mV
000H
FFFH
Figure 22. Endpoint Nonlinearities Due to Amplifier
Saturation
The endpoint nonlinearities conceptually illustrated in Figure 22
get worse as a function of output loading. Most of the ADuC832
s
specifications assume a 10 k
resistive load to ground at the
DAC output. As the output is forced to source or sink more
current, the nonlinear regions at the top or bottom (respectively)
of Figure 22 become larger. With larger current demands, this
can significantly limit output voltage swing. Figures 23 and 24
illustrate this behavior. It should be noted that the upper trace in
each of these figures is only valid for an output range selection
of 0-to-AV
DD
. In 0-to-V
REF
mode, DAC loading will not cause
highside voltage drops as long as the reference voltage remains
below the upper trace in the corresponding figure. For example,
if AV
DD
= 3 V and V
REF
= 2.5 V, the high side voltage will not be
affected by loads less than 5 mA. But somewhere around 7 mA,
the upper curve in Figure 24 drops below 2.5 V (V
REF
), indicating
that at these higher currents the output will not be capable of
reaching V
REF
.
SOURCE/SINK CURRENT – mA
5
0
5
10
15
O
4
3
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
Figure 23. Source and Sink Current Capability with
V
REF
= V
DD
= 5 V
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