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參數(shù)資料
| 型號： | ADUC832BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | MO-112AC-1, MQFP-52 |
| 文件頁數(shù)： | 41/80頁 |
| 文件大?。?/td> | 1311K |
| 代理商： | ADUC832BCP |
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REV. 0
ADuC832
–41–
I
2
C COMPATIBLE INTERFACE
The ADuC832 supports a fully licensed
*
I
2
C serial interface. The
I
2
C interface is implemented as a full hardware slave and software
master. SDATA is the data I/O pin and SCLOCK is the serial
clock. These two pins are shared with the MOSI and SCLOCK
pins of the on-chip SPI interface. Therefore, the user can only
enable one or the other interface at any given time (see SPE in
SPICON previously). Application Note uC001 describes the
operation of this interface as implemented is available from the
MicroConverter website at www.analog.com/microconverter.
Three SFRs are used to control the I
2
C interface. These are described below:
I2CCON
SFR Address
Power-On Default Value
Bit Addressable
I
2
C Control Register
E8H
00H
Yes
Table XIII. I2CCON SFR Bit Designations
Bit
Name
Description
I
2
C Software Master Data Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to this
bit will be output on the SDATA pin if the data output enable (MDE) bit is set.
I
2
C Software Master Data Output Enable Bit (Master Mode Only).
Set by user to enable the SDATA pin as an output (Tx).
Cleared by the user to enable SDATA pin as an input (Rx).
I
2
C Software Master Clock Output Bit (Master Mode Only).
This data bit is used to implement a master I
2
C transmitter interface in software. Data written to
this bit will be output on the SCLOCK pin.
I
2
C Software Master Data Input Bit (Master Mode Only).
This data bit is used to implement a master I
2
C receiver interface in software. Data on the SDATA
pin is latched into this bit on SCLOCK if the Data Output Enable (MDE) bit is
“
0.
”
I
2
C Master/Slave Mode Bit
Set by user to enable I
2
C software master mode.
Cleared by user to enable I
2
C hardware slave mode.
I
2
C Reset Bit (Slave Mode Only).
Set by user to reset the I
2
C interface.
Cleared by user code for normal I
2
C operation.
I
2
C Direction Transfer Bit (Slave Mode Only).
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
2
C Interrupt Bit (Slave Mode Only).
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
7
MDO
6
MDE
5
MCO
4
MDI
3
I2CM
2
I2CRS
1
I2CTX
0
I2CI
I2CADD
Function
I
2
C Address Register
Holds the I
2
C peripheral address for the part. It may be overwritten by user code. Technical Note uC001
at www.analog.com/microconverter describes the format of the I
2
C standard 7-bit address in detail.
9BH
55H
No
SFR Address
Power-On Default Value
Bit Addressable
I2CDAT
Function
I
2
C Data Register
The I2CDAT SFR is written by the user to transmit data over the I
2
C
read data just received by the I
2
C interface. Accessing I2CDAT automatically clears any pending I
2
C
interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per
interrupt cycle.
9AH
00H
No
interface or read by user code to
SFR Address
Power-On Default Value
Bit Addressable
*
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I
2
C Patent
Rights to use the ADuC832 in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
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