參數(shù)資料
型號(hào)： ADUC832BCP
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述： 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝： MO-112AC-1, MQFP-52
文件頁(yè)數(shù)： 31/80頁(yè)
文件大小： 1311K
代理商： ADUC832BCP
REV. 0
ADuC832
–31–
ADuC832 Configuration SFR (CFG832)
The CFG832 SFR contains the necessary bits to configure the
internal XRAM, External Clock select, PWM output selection,
DAC buffer, and the extended SP. By default it configures the
user into 8051 mode, i.e., extended SP is disabled, internal
XRAM is disabled.
CFG832
SFR Address
Power-On Default Value
Bit Addressable
ADuC832 Config SFR
AFH
00H
No
Table VIII. CFG832 SFR Bit Designations
Bit
Name
Description
7
EXSP
Extended SP Enable.
When set to
“
1
”
by the user, the stack will roll over from SPH/SP = 00FFH to 0100H.
When set to
“
0
”
by the user, the stack will roll over from SP = FFH to SP = 00H.
PWM pin out selection
Set to
“
1
”
by the user = PWM output pins selected as P3.4 and P3.3.
Set to
“
0
”
by the user = PWM output pins selected as P2.6 and P2.7.
DAC Output Buffer
Set to
“
1
”
by the user = DAC
.
Output Buffer Bypassed.
Set to
“
0
”
by the user = DAC Output Buffer Enabled.
Set by the user to
“
1
”
to select an external clock input on P3.4.
Set by the user to
“
0
”
to use the internal PLL clock.
Reserved
–
This bit should always contain 0.
Reserved
–
This bit should always contain 0.
Reserved
–
This bit should always contain 0.
XRAM Enable Bit
When set to
“
1
”
by the user, the internal XRAM will be mapped into the lower 2 kBytes of the external
address space.
When set to
“
0
”
by the user, the internal XRAM will not be accessible and the external data memory
will be mapped into the lower 2 kBytes of external data memory.
6
PWPO
5
DBUF
4
EXTCLK
3
2
1
0
RSVD
RSVD
RSVD
XRAMEN
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