參數(shù)資料
型號(hào)： ADUC832BCP
廠商： ANALOG DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述： 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝： MO-112AC-1, MQFP-52
文件頁(yè)數(shù)： 59/80頁(yè)
文件大小： 1311K
代理商： ADUC832BCP
REV. 0
ADuC832
–59–
Timer 3 Generated Baud Rates
The high integer dividers in a UART block mean that high speed
baud rates are not always possible using some particular crystals.
For example, using a 12 MHz crystal, a baud rate of 115200 is
not possible. To address this problem, the ADuC832 has added
a dedicated baud rate timer (Timer 3) specifically for generating
highly accurate baud rates.
Timer 3 can be used instead of Timer 1 or Timer 2 for generating
very accurate high speed UART baud rates including 115200
and 230400. Timer 3 also allows a much wider range of baud
rates to be obtained. In fact, every desired bit rate from 12 bit/s
to 393216 bit/s can be generated to within an error of
±
0.8%.
Timer 3 also frees up the other three timers, allowing them to
be used for different applications. A block diagram of Timer 3
is shown in Figure 54.
(1 + T3FD/64)
2
T3 RX/TX
CLOCK
CORE
CLK
*
T3EN
RX
CLOCK
TX CLOCK
TIMER 1/TIMER 2
RX CLOCK (FIG 53)
FRACTIONAL
DIVIDER
0
0
1
1
TIMER 1/TIMER 2
TX CLOCK (FIG 53)
16
2
DIV
*
CORE CLK IS DEFINED BY THE CD BITS IN PLLCON
Figure 54. Timer 3, UART Baud Rates
Two SFRs (T3CON and T3FD) are used to control Timer 3.
T3CON is the baud rate control SFR, allowing Timer 3 to be
used to set up the UART baud rate, and setting up the binary
divider (DIV).
Table XXVII. T3CON SFR Bit Designations
Bit
Name
Description
7
T3BAUDEN
T3UARTBAUD Enable
Set to enable Timer 3 to generate
the baud rate. When set PCON.7,
T2CON.4 and T2CON.5 are ignored.
Cleared to let the baud rate be
generated as per a standard 8052.
-
-
-
-
Binary Divider Factor
DIV2 DIV1 DIV0 Bin Divider
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
6
5
4
3
2
1
0
DIV2
DIV1
DIV0
The appropriate value to write to the DIV2-1-0 bits can be calculated
using the following formula where
f
CORE
defined in PLLCON SFR:
Note: The DIV value must be rounded down.
DIV
f
CORE
Baud Rate
=
×
log( )
log
32
2
T3FD is the fractional divider ratio required to achieve the
required baud rate. We can calculate the appropriate value for
T3FD using the following formula:
Note: T3FD should be rounded to the nearest integer.
T FD
3
f
Baud Rate
CORE
DIV
2
2
=
×
×
Once the values for DIV and T3FD are calculated the actual
baud rate can be calculated using the following formula:
Actual Baud Rate
=
×
T FD
(
×
+
2
2
3
64
f
CORE
DIV
)
For example, to get a baud rate of 115200 while operating at
16.7 MHz
(
=
(
3
2 11059200
2
/
DIV
LOG
LOG
T FD
H
=
)
(
)
–
=
=
)
×
(
)
=
=
11059200
32 115200
2
1 58
.
1
115200
64
32
20
1
/
/
therefore, the actual baud rate is 114912 bit/s.
Table XXVIII. Commonly Used Baud Rates Using Timer 3
Ideal
Baud
%
Error
CD
DIV
T3CON
T3FD
230400
0
1
81H
09H
0.25
115200
115200
115200
0
1
2
2
1
0
82H
81H
80H
09H
09H
09H
0.25
0.25
0.25
57600
57600
57600
57600
0
1
2
3
3
2
1
0
83H
82H
81H
80H
09H
09H
09H
09H
0.25
0.25
0.25
0.25
38400
38400
38400
38400
0
1
2
3
3
2
1
0
83H
82H
81H
80H
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
19200
19200
19200
19200
19200
0
1
2
3
4
4
3
2
1
0
84H
83H
82H
81H
80H
2DH
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
0.2
9600
9600
9600
9600
9600
9600
0
1
2
3
4
5
5
4
3
2
1
0
85H
84H
83H
82H
81H
80H
2DH
2DH
2DH
2DH
2DH
2DH
0.2
0.2
0.2
0.2
0.2
0.2
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