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參數(shù)資料
| 型號： | ADUC832BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU |
| 中文描述： | 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | MO-112AC-1, MQFP-52 |
| 文件頁數(shù)： | 6/80頁 |
| 文件大小： | 1311K |
| 代理商： | ADUC832BCP |
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REV. 0
–6–
ADuC832
SPECIFICATIONS
(continued)
NOTES
Temperature Range
–
40
o
C to +125
o
C.
2
ADC linearity is guaranteed during normal MicroConverter core operation.
3
ADC LSB Size = V
/2
i.e., for Internal V
= 2.5 V, 1 LSB = 610
μ
V and for External V
= 1 V, 1 LSB = 244
μ
V.
4
These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
5
Offset and Gain Error and Offset and Gain Error Match are measured after factory calibration.
6
Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these
specifications.
7
SNR calculation includes distortion and noise components.
8
Channel-to-channel crosstalk is measured on adjacent channels.
9
The Temperature Monitor will give a measure of the die temperature directly; air temperature can be inferred from this result.
10
DAC linearity is calculated using:
Reduced code range of 100 to 4095, 0 to V
REF
range.
Reduced code range of 100 to 3945, 0 to V
DD
range.
DAC Output Load = 10 k
and 100 pF.
11
DAC differential nonlinearity specified on 0 to V
and 0 to V
ranges.
12
DAC specification for output impedance in the unbuffered case depends on DAC code.
13
DAC specifications for I
, voltage output settling time and digital-to-analog glitch energy depend on external buffer implementation in unbuffered mode. DAC in
unbuffered mode tested with OP270 external buffer, which has a low input leakage current.
14
Measured with V
and C
pins decoupled with 0.1
μ
F capacitors to ground. Power-up time for the internal reference will be determined by the value of the
decoupling capacitor chosen for both the V
and C
pins.
15
When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the V
REF
and C
REF
pins need to be shorted together for correct operation.
16
Flash/EE Memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
17
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at
–
40
o
C, +25
o
C, and +125
o
C. Typical endurance at 25
o
C is 700,000 cycles.
18
Retention lifetime equivalent at junction temperature (T
) = 55
o
C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 eV
will derate with junction temperature as shown in Figure 18 in the Flash/EE Memory description section.
19
Power supply current consumption is measured in Normal, Idle, and Power-Down Modes under the following conditions:
Normal Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop.
Idle Mode:
Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in
idle mode.
Power-Down Mode:
Reset = 0.4 V, All Port 0 pins = 0.4 V, All other digital I/O and Port 1 pins are open circuit, Core Clk changed via CD bits in PLLCON,
PCON.0 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR
20
DV
DD
power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
Specifications subject to change without notice.
Parameter
POWER REQUIREMENTS
19, 20
Power Supply Voltages
AV
DD
/DV
DD
–
AGND
V
DD
= 5 V
V
DD
= 3 V
Unit
Test Conditions/Comments
2.7
3.3
V min
V max
V min
V max
AV
DD
/DV
DD
= 3 V nom
4.5
5.5
AV
DD
/DV
DD
= 5 V nom
Power Supply Currents Normal Mode
DV
DD
Current
4
AV
DD
Current
DV
DD
Current
6
1.7
23
20
1.7
3
1.7
12
10
1.7
mA max
mA max
mA max
mA typ
mA max
Core CLK = 2.097 MHz
Core CLK = 2.097 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
AV
DD
Current
Power Supply Currents Idle Mode
DV
DD
Current
AV
DD
Current
DV
DD
Current
4
4
0.14
10
9
0.14
2
0.14
5
4
0.14
mA typ
mA typ
mA max
mA typ
mA typ
Core CLK = 2.097 MHz
Core CLK = 2.097 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 16.78 MHz
Core CLK = 2.097 MHz or 16.78 MHz
Osc. On
AV
DD
Current
Power Supply Currents Power-Down Mode
DV
DD
Current
4
80
38
2
35
25
25
14
1
20
12
μ
A max
μ
A typ
μ
A typ
μ
A max
μ
A typ
AV
DD
Current
DV
DD
Current
Osc. Off
Typical Additional Power Supply Currents
PSM Peripheral
ADC
DAC
AV
DD
= DV
DD
= 5 V
50
1.5
150
μ
A typ
mA typ
μ
A typ
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|---|---|
| ADUC832BCP-REEL | 制造商:Analog Devices 功能描述:MCU 8-Bit ADuC8xx 8052 CISC 62KB Flash 3V/5V 56-Pin LFCSP EP T/R |
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