參數(shù)資料
型號： ADUC832BCP
廠商： ANALOG DEVICES INC
元件分類： 微控制器/微處理器
英文描述： MicroConverter, 12-Bit ADCs and DACs with Embedded 62 kBytes Flash MCU
中文描述： 8-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP52
封裝： MO-112AC-1, MQFP-52
文件頁數(shù)： 29/80頁
文件大?。?/td> 1311K
代理商： ADUC832BCP
REV. 0
ADuC832
–29–
Table VII. ECON—Flash/EE Memory Commands
COMMAND DESCRIPTION
(NORMAL MODE) (Power-On Default)
COMMAND DESCRIPTION
(ULOAD MODE)
ECON VALUE
01H
READ
Results in four bytes in the Flash/EE data memory, addressed Not Implemented. Use the MOVC instruction.
by the page address EADRH/L, being read into EDATA 1 to 4.
02H
WRITE
Results in four bytes in EDATA1
–
4 being written to
the Flash/EE data memory at the page address given
by EADRH/L (0
≤
EADRH / L < 0400H).
Note: The four bytes in the page being addressed must
be pre-erased.
Results in bytes 0
–
255 of internal XRAM being written
to the 256 bytes of Flash/EE program memory at the
page address given by EADRH (0
≤
EADRH < E0H).
Note: The 256 bytes in the page being addressed
must be pre-erased.
03H
Reserved Command
Reserved Command
04H
VERIFY
Verifies if the data in EDATA1
–
4 is contained in the page
address given by EADRH/L. A subsequent read of the
ECON SFR will result in a 0 being read if the verification is valid,
or a nonzero value being read to indicate an invalid verification.
Not Implemented. Use the MOVC and MOVX
Instructions to verify the WRITE in software.
05H
ERASE PAGE
Results in the Erase of the 4-byte page of Flash/EE data
memory addressed by the page address EADRH/L.
Results in the 64-byte page of Flash/EE program memory,
addressed by the byte address EADRH/L being erased.
EADRL can equal any of 64 locations within the page.
A new page starts whenever EADRL is equal to 00H,
40H, 80H, or C0H.
06H
ERASE ALL
Results in the erase of entire 4 kBytes of Flash/EE
data memory.
Results in the Erase of the entire 56 kBytes of ULOAD
Flash/EE program memory.
81H
READBYTE
Results in the byte in the Flash/EE data memory, addressed
by the byte address EADRH/L, being read into EDATA1
(0
≤
EADRH / L
≤
0FFFH).
Not Implemented. Use the MOVC command.
82H
WRITEBYTE
Results in the byte in EDATA1 being written into
Flash/EE data memory, at the byte address EADRH/L.
Results in the byte in EDATA1 being written into
Flash/EE program memory, at the byte address
EADRH/L (0
≤
EADRH / L
≤
DFFFH).
0FH
EXULOAD
Leaves the ECON instructions to operate on the Flash/EE
data memory.
Enters NORMAL mode directing subsequent ECON
instructions to operate on the Flash/EE data memory.
F0H
ULOAD
Enters ULOAD mode, directing subsequent ECON
instructions to operate on the Flash/EE program memory.
Leaves the ECON instructions to operate on the
Flash/EE program memory.
USING THE FLASH/EE DATA MEMORY
The 4 kBytes of Flash/EE data memory is configured as 1024
pages, each of four bytes. As with the other ADuC832 peripherals,
the interface to this memory space is via a group of registers
mapped in the SFR space. A group of four data registers
(EDATA1
–
4) are used to hold the four bytes of data at each
page. The page is addressed via the two registers EADRH and
EADRL. Finally, ECON is an 8-bit control register that may be
written with one of nine Flash/EE memory access commands to
trigger various read, write, erase, and verify functions.
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 20.
ECON—Flash/EE Memory Control SFR
Programming of either the Flash/EE data memory or the Flash/EE
program memory is done through the Flash/EE memory control
SFR (ECON). This SFR allows the user to read, write, erase, or
verify the 4 kBytes of Flash/EE data memory or the 56 kBytes
of Flash/EE program memory.
BYTE 1
(0000H)
E
BYTE 1
(0004H)
BYTE 1
(0008H)
BYTE 1
(000CH)
BYTE 1
(0FF8H)
BYTE 1
(0FFCH)
BYTE 2
(0001H)
E
BYTE 2
(0005H)
BYTE 2
(0009H)
BYTE 2
(000DH)
BYTE 2
(0FF9H)
BYTE 2
(0FFDH)
BYTE 3
(0002H)
E
BYTE 3
(0006H)
BYTE 3
(000AH)
BYTE 3
(000EH)
BYTE 3
(0FFAH)
BYTE 3
(0FFEH)
BYTE 4
(0003H)
E
BYTE 4
(0007H)
BYTE 4
(000BH)
BYTE 4
(000FH)
BYTE 4
(0FFBH)
BYTE 4
(0FFFH)
01H
00H
02H
03H
3FEH
3FFH
P
(
BYTE
ADDRESSES
ARE GIVEN IN
BRACKETS
Figure 20. Flash/EE Data Memory Control and Configuration
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