參數(shù)資料
型號： ADUC7036DCPZ-RL
廠商： Analog Devices Inc
文件頁數(shù)： 81/132頁
文件大?。?/td> 0K
描述： IC MCU 96K FLASH DUAL 48LFCSP
標準包裝： 2,500
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 帶卷 (TR)
ADuC7036
Rev. C | Page 52 of 132
ADC Configuration Register
Name: ADCCFG
Address: 0xFFFF051C
Default Value: 0x00
Access: Read/write
Function: This 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs.
Table 42. ADCCFG MMR Bit Designations
Bit
Description
7
Analog ground switch enable.
Set to 1 by user software to connect the external GND_SW pin (Pin 15) to an internal analog ground reference point. This bit can
be used to connect and disconnect external circuits and components to ground under program control and, thereby, minimize dc
current consumption when the external circuit or component is not used. This bit is used in conjunction with ADCMDE[6] to select
a 20 kΩ resistor to ground.
Cleared by user code to disconnect the external GND_SW pin.
6, 5
Current channel (32-bit) accumulator enable.
00 = accumulator disabled and reset to 0. The accumulator must be disabled for a full ADC conversion (ADCSTA[0] set twice)
before the accumulator can be reenabled to ensure that the accumulator is reset.
01 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535
conversions.
Negative current values are subtracted from the accumulator total; the accumulator is clamped to a minimum value of 0.
10 = accumulator active.
Positive current values are added to the accumulator total; the accumulator can overflow if allowed to run for >65,535 conversions.
The absolute values of negative current are subtracted from the accumulator total; the accumulator in this mode continues to
accumulate negatively, below 0.
11 = not defined.
4, 3
Current channel ADC comparator enable.
00 = comparator disabled.
01 = comparator active, interrupt asserted if absolute value of I-ADC conversion result is |I| ≥ ADC0TH.
10 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result is |I| ≥ ADC0TH for the
number of ADC0TCL conversions. A conversion value of |I| < ADC0TH resets the threshold counter value (ADC0THV) to 0.
11 = comparator count mode active, interrupt asserted if absolute value of an I-ADC conversion result is |I| ≥ ADC0TH for the
number of ADC0TCL conversions. A conversion value of |I| < ADC0TH decrements the threshold counter value (ADC0THV) toward 0.
2
Current channel ADC overrange enable.
Set by user to enable a coarse comparator on the current channel ADC. If the current reading is grossly (>30% approximate)
overrange for the active gain setting, then the overrange bit in the ADCSTA MMR is set.
The current must be outside this range for greater than 125 μs for the flag to be set. This feature should not be used in ADC low
power mode.
Cleared by user code to disable the overrange feature.
1
Not used. This bit is reserved for future functionality and should be written as 0 by user code.
0
Current channel ADC, result counter enable.
Set by user to enable the result count mode. In this mode, an I-ADC interrupt is generated only when ADC0RCV = ADC0RCL. This
allows the I-ADC to continuously monitor current but only interrupt the MCU core after a defined number of conversions. The
voltage/temperature ADC also continues to convert if enabled, but again, only the last conversion result is available (intermediate
V-/T-ADC conversion results are not stored) when the ADC counter interrupt occurs.
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