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參數(shù)資料
| 型號： | ADSP-2192M |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | DSP微機(jī) |
| 文件頁數(shù)： | 3/40頁 |
| 文件大?。?/td> | 1307K |
| 代理商： | ADSP-2192M |
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ADSP-2192M
GENERAL DESCRIPTION
The ADSP-2192M is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications, and is ideally suited for PC peripherals.
The ADSP-2192M combines the ADSP-219x family base archi-
tecture (three computational units, two data address generators
and a program sequencer) into a chip with two core processors
(see the Functional Block Diagram
on Page 1
and
Figure 1
).
The ADSP-2192M includes a PCI-compatible port, a USB-
compatible port, an AC’97-compatible port, a DMA controller,
a programmable timer, general-purpose Programmable Flag
pins, extensive interrupt capabilities, and on-chip program and
data memory spaces.
The ADSP-2192M integrates 132K words of on-chip memory
configured as 32K words (24-bit) of program RAM, and 100K
words (16-bit) of data RAM. power-down circuitry is also
provided to reduce power consumption. The ADSP-2192M is
available in a 144-lead LQFP package.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2192M operates with a 6.25 ns instruction cycle time
(320 MIPS) using both cores. All instructions can execute in a
single DSP cycle.
The ADSP-2192M’s flexible architecture and comprehensive
instruction set support multiple operations in parallel. For
example, in one processor cycle, each DSP core within the
ADSP-2192M can:
Generate an address for the next instruction fetch
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computational operation
These operations take place while the processor continues to:
Receive and/or transmit data through the Host port (PCI
or USB interfaces)
Receive or transmit data through the AC’97
Decrement the two timers
DSP Core Architecture
The ADSP-219x architecture is code compatible with the ADSP-
218x DSP family. Though the architectures are compatible, the
ADSP-219x architecture has many enhancements over the
ADSP-218x architecture. The enhancements to computational
units, data address generators, and program sequencer make the
ADSP-219x more flexible and more compiler friendly.
Indirect addressing options provide addressing flexibility: base
address registers for easier implementation of circular buffering,
pre-modify with no update, post-modify with update, pre- and
post-modify by an immediate 8-bit, twos-complement value.
The ADSP-219x instruction set provides flexible data moves and
multifunction (one or two data moves with a computation)
instructions. Every single-word instruction can be executed in a
single processor cycle. The ADSP-219x assembly language uses
an algebraic syntax for ease of coding and readability. A compre-
hensive set of development tools supports program development.
The Functional Block Diagram
on Page 1
shows the architecture
of the ADSP-219x dual core DSP, while the block diagram of
Figure 1
illustrates the ADSP-219x DSP core. Each core
contains three independent computational units: the multi-
plier/accumulator (MAC), the ALU, and the shifter. The
computational units process 16-bit data from the register file and
have provisions to support multiprecision computations. The
ALU performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract oper-
ations. The MAC has two 40-bit accumulators that help with
overflow. The shifter performs logical and arithmetic shifts, nor-
malization, denormalization, and derive exponent operations.
The shifter can be used to efficiently implement numeric format
control, including multiword and block floating-point
representations.
Register-usage rules influence placement of input and results
within the computational units. For most operations, the com-
putational units’ data registers act as a data register file,
permitting any input or result register to provide input to any unit
for a computation. For feedback operations, the computational
units let the output (result) of any unit be input to any unit on
Figure 1. ADSP-219x DSP Core
CACHE
64
24-BIT
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
24
16
DSP CORE
PROGRAM
SEQUENCER
DATA
REGISTER
FILE
MULT
BARREL
SHIFTER
ALU
INPUT
REGISTERS
RESULT
REGISTERS
16
16-BIT
CORE
INTERFACE
DAG1
4
4
16
24
24
DAG2
4
4
16
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