參數(shù)資料
型號： ADSP-2192M
廠商： Analog Devices, Inc.
元件分類： 數(shù)字信號處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁數(shù)： 27/40頁
文件大小： 1307K
代理商： ADSP-2192M
–27–
REV. 0
ADSP-2192M
Target Board Header
The emulator interface to an Analog Devices JTAG DSP is a
14-pin header, as shown in
Figure 9
. The customer must supply
this header on the target board in order to communicate with the
emulator. The interface consists of a standard dual row 0.025"
square post header, set on 0.1"
post length of 0.235". Pin 3 is the key position used to prevent
the pod from being inserted backwards. This pin must be clipped
on the target board.
0.1" spacing, with a minimum
Also, the clearance (length, width, and height) around the header
must be considered. Leave a clearance of at least 0.15" and 0.10"
around the length and width of the header, and reserve a height
clearance to attach and detach the pod connector.
As can be seen in
Figure 9
, there are two sets of signals on the
header. There are the standard JTAG signals TMS, TCK, TDI,
TDO,
TRST
, and
EMU
used for emulation purposes (via an
emulator). There are also secondary JTAG signals BTMS,
BTCK, BTDI, and
BTRST
that are optionally used for board-
level (boundary scan) testing.
When the emulator is not connected to this header, place jumpers
across BTMS, BTCK,
BTRST
, and BTDI as shown in
Figure 10
. This holds the JTAG signals in the correct state to
allow the DSP to run free. Remove all the jumpers when con-
necting the emulator to the JTAG header.
JTAG Emulator Pod Connector
Figure 11
details the dimensions of the JTAG pod connector at
the 14-pin target end.
Figure 12
displays the keep-out area for a
target board header. The keep-out area allows the pod connector
to properly seat onto the target board header. This board area
should contain no components (such as chips, resistors, capaci-
tors). The dimensions are referenced to the center of the 0.25"
square post pin.
Design-for-Emulation Circuit Information
For details on target board design issues including: single
processor connections, multiprocessor scan chains, signal buff-
ering, signal termination, and emulator pod logic, see the
EE-68:
Analog Devices
J
TAG Emulation Technical Reference
on the Analog
www.analog.com
improvements to emulator support.
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