參數(shù)資料
型號(hào)： ADSP-2192M
廠(chǎng)商： Analog Devices, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DSP Microcomputer
中文描述： DSP微機(jī)
文件頁(yè)數(shù)： 14/40頁(yè)
文件大小： 1307K
代理商： ADSP-2192M
ADSP-2192M
–14–
REV. 0
USB DSP Register Definitions
For each endpoint, four registers are defined to provide a memory
buffer in the DSP. These registers are defined for each endpoint
shared by all defined interfaces, for a total of 4 8 = 32 registers.
These registers are read/write by the DSP only. They are
described in
Table 11
.
USB DSP Memory Buffer Base Addr Register
Points to the base address for the DSP memory buffer assigned
to this endpoint.
BA[17:0] = Memory Buffer Base Address
USB DSP Memory Buffer Size Register
Indicates the size of the DSP memory buffer assigned to this
endpoint.
SZ[15:0] = Memory Buffer Size
USB DSP Memory Buffer RD Pointer Offset Register
The offset from the base address for the read pointer of the
memory buffer assigned to this endpoint.
RD[15:0] = Memory Buffer RD Offset
USB DSP Memory Buffer WR Pointer Offset Register
The offset from the base address for the write pointer of the
memory buffer assigned to this endpoint.
WR[15:0] = Memory Buffer WR Offset
Table 10. 16-Bit PCI DSP I/O Space Indirect Access
Registers Map (BAR4 Mode)
Offset
Name
Reset
Comments
0x03–0x00 Control
Register
Address
0x0000
Address and direction
control for register
accesses
Data for register
accesses
0x07–0x04 Control
Register
Data
0x0000
0x0B–0x08 DSP
Memory
Address
0x000000 Address and Direction
control for Indirect
DSP memory accesses
0x000000 Data for DSP memory
accesses
0x0F–0x0C DSP
Memory
Data
Table 11. USB DSP Register Definitions
Page Address
Name
Comment
0x0C 0x0–0x3
DSP Memory Buffer Base
Addr
DSP Memory Buffer Size EP4
DSP Memory Buffer RD
Offset
DSP Memory Buffer WR
Offset
EP4
0x0C 0x4–0x5
0x0C 0x6–0x7
EP4
0x0C 0x8–0x9
EP4
0x0C 0x10–0x13 DSP Memory Buffer Base
Addr
0x0C 0x14–0x15 DSP Memory Buffer Size EP5
0x0C 0x16–0x17 DSP Memory Buffer RD
Offset
0x0C 0x18–0x19 DSP Memory Buffer WR
Offset
0x0C 0x20–0x23 DSP Memory Buffer Base
Addr
0x0C 0x24–0x25 DSP Memory Buffer Size EP6
0x0C 0x26–0x27 DSP Memory Buffer RD
Offset
0x0C 0x28–0x29 DSP Memory Buffer WR
Offset
0x0C 0x30–0x33 DSP Memory Buffer Base
Addr
0x0C 0x34–0x35 DSP Memory Buffer Size EP7
0x0C 0x36–0x37 DSP Memory Buffer RD
Offset
0x0C 0x38–0x39 DSP Memory Buffer WR
Offset
0x0C 0x40–0x43 DSP Memory Buffer Base
Addr
0x0C 0x44–0x45 DSP Memory Buffer Size EP8
EP5
EP5
EP5
EP6
EP6
EP6
EP7
EP7
EP7
EP8
0x0C 0x46–0x47 DSP Memory Buffer RD
Offset
0x0C 0x48–0x49 DSP Memory Buffer WR
Offset
0x0C 0x50–0x53 DSP Memory Buffer Base
Addr
0x0C 0x54–0x55 DSP Memory Buffer Size EP9
0x0C 0x56–0x57 DSP Memory Buffer RD
Offset
0x0C 0x58–0x59 DSP Memory Buffer WR
Offset
0x0C 0x60–0x63 DSP Memory Buffer Base
Addr
0x0C 0x64–0x65 DSP Memory Buffer Size EP10
0x0C 0x66–0x67 DSP Memory Buffer RD
Offset
0x0C 0x68–0x69 DSP Memory Buffer WR
Offset
0x0C 0x70–0x73 DSP Memory Buffer Base
Addr
0x0C 0x74–0x75 DSP Memory Buffer Size EP11
0x0C 0x76–0x77 DSP Memory Buffer RD
Offset
0x0C 0x78–0x79 DSP Memory Buffer WR
Offset
0x0C 0x80–0x81 USB Descriptor Vendor
ID
0x0C 0x84–0x85 USB Descriptor Product
ID
0x0C 0x86–0x87 USB Descriptor Release
Number
0x0C 0x88–0x89 USB Descriptor Device
Attributes
EP8
EP8
EP9
EP9
EP9
EP10
EP10
EP10
EP11
EP11
EP11
Table 11. USB DSP Register Definitions (continued)
Page Address
Name
Comment
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