- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄364639 > ADS1286P Analog-to-Digital Converter??? 12-Bit PDF資料下載
參數(shù)資料
| 型號： | ADS1286P |
| 元件分類： | ADC |
| 英文描述： | Analog-to-Digital Converter??? 12-Bit |
| 中文描述： | 12位模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 21/42頁 |
| 文件大?。?/td> | 872K |
| 代理商： | ADS1286P |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
ADS1212, 1213
SBAS064A
21
Table XI. Decimation Ratios for Various Data Rates (Turbo Mode Rate of 1 and 1MHz clock).
CH1
CH0
ACTIVE INPUT
0
0
1
1
0
1
0
1
Channel 1
Channel 2
Channel 3
Channel 4
Default
TURBO
MODE
RATE
AVAILABLE
PGA
SETTINGS
SF2
SF1
SF0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
1
Default
Most Significant Bit
Byte 2
DOR23
DOR22
DOR21
DOR20
DOR19
DOR18
DOR17
DOR16
Byte 1
DOR15
DOR14
DOR13
DOR12
DOR11
DOR10
DOR9
DOR8
Byte 0
Least Significant Bit
DOR7
DOR6
DOR5
DOR4
DOR3
DOR2
DOR1
DOR0
TABLE XII. Data Output Register.
G2-G0 (PGA Control) Bits—
The G2-G0 bits control the
gain setting of the PGA, as follows:
GAIN
SETTING
AVAILABLE TURBO
MODE RATES
G2
G1
G0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
2
4
8
16
1, 2, 4, 8, 16
1, 2, 4, 8
1, 2, 4
1, 2
1
Default
The gain is partially implemented by increasing the input
capacitor sampling frequency, which is given by the follow-
ing equation:
f
SAMP
= G TMR f
XIN
/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The product of G and TMR cannot exceed 16. The
sampling frequency of the input capacitor directly relates to
the analog input impedance. See the Programmable Gain
Amplifier and Analog Input sections for more details.
CH1-CH0 (Channel Selection) Bits—
The CH1 and CH0 bits
control the input multiplexer on the ADS1213, as follows:
(For the ADS1212, CH1 and CH0 must always be zero.) The
channel change takes effect when the last bit of byte 2 has
been written to the Command Register. Output data will not
be valid for the next three conversions despite the DRDY
signal indicating that data is ready. On the fourth time that
DRDY goes LOW after a channel change has been written
to the Command Register, valid data will be present in the
Data Output Register (see Figure 4).
SF2-SF0 (Turbo Mode Rate) Bits—
The SF2-SF0 bits
control the input capacitor sampling frequency and modula-
tor rate, as follows:
The input capacitor sampling frequency and modulator rate
can be calculated from the following equations:
f
SAMP
= G TMR f
XIN
/128
f
MOD
= TMR f
XIN
/128
where G is the gain setting and TMR is the Turbo Mode
Rate. The sampling frequency of the input capacitor directly
relates to the analog input impedance. The modulator rate
relates to the power consumption of the ADS1212/13 and
the output data rate. See the Turbo Mode, Analog Input, and
Reference Input sections for more details.
DR12-DR0 (Decimation Ratio) Bits—
The DR12-DR0 bits
control the decimation ratio of the ADS1212/13. In essence,
these bits set the number of modulator results which are used in
the digital filter to compute each individual conversion result.
Since the modulator rate depends on both the ADS1212/13
clock frequency and the Turbo Mode Rate, the actual output
data rate is given by the following equation:
f
DATA
= f
XIN
TMR/(128 (Decimation Ratio + 1))
where TMR is the Turbo Mode Rate. Table XI shows
various data rates and corresponding decimation ratios (with
a 1MHz clock). Valid decimation ratios are from 19 to 8000.
Outside of this range, the digital filter will compute results
incorrectly due to inadequate or too much data.
Data Output Register (DOR)
The DOR is a 24-bit register which contains the most recent
conversion result (see Table XII). This register is updated
with a new result just prior to DRDY going LOW. If the
contents of the DOR are not read within a period of time
defined by 1/f
DATA
–24(1/f
XIN
), then a new conversion
result will overwrite the old. (DRDY is forced HIGH prior
to the DOR update, unless a read is in progress).
The contents of the DOR can be in Two’s Complement or
Offset Binary format. This is controlled by the DF bit of the
Command Register. In addition, the contents can be limited to
unipolar data only with the U/B bit of the Command Register.
Data
Rate
(Hz)
Deci-
mation
Ratio
DR12
DR11
DR10
DR9
DR8
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
391
250
100
60
50
20
10
0.96
19
30
77
129
155
390
780
8000
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
0
1
0
1
1
1
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADS1286PA | Analog-to-Digital Converter??? 12-Bit |
| ADS1286PB | Analog-to-Digital Converter??? 12-Bit |
| ADS1286PC | Analog-to-Digital Converter??? 12-Bit |
| ADS1286PK | Analog-to-Digital Converter??? 12-Bit |
| ADS1286PL | Analog-to-Digital Converter??? 12-Bit |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADS1286P | 制造商:Texas Instruments 功能描述:IC 12BIT ADC 200 KHZ PDIP8 1286 |
| ADS1286PA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KHz Unipol RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1286PA | 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 1286 DIP8 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi |
| ADS1286PAG4 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B Micro Pwr Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADS1286PB | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Micro Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。