參數(shù)資料
型號： ADS1286P
元件分類： ADC
英文描述： Analog-to-Digital Converter??? 12-Bit
中文描述： 12位模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 14/42頁
文件大?。?/td> 872K
代理商： ADS1286P
ADS1212, 1213
SBAS064A
14
Valid
Data
DRDY
Serial
I/O
Valid
Data
SOC
(1)
t
DATA
Normal
Mode
Offset
Calibration on
System Offset
(2)
Analog
Input
Conversion
System Offset
Calibration Mode
Possibly
Valid
Data
Possibly
Valid
Data
Normal
Mode
NOTES: (1) SOC = System Offset Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
FIGURE 5. Self-Calibration Timing.
Mode bits are reset to 000 (Normal Mode). A single conver-
sion is done with DRDY HIGH. After this conversion, the
DRDY signal goes LOW indicating resumption of normal
operation.
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the offset calibration
is performed. In this case, the digital filter already contains
a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. In addition, the
offset calibration error will be the rms sum of the conversion
error and the noise on the system offset voltage. See the
System Calibration Limits section for information regarding
the limits on the magnitude of the system offset voltage.
System Full-Scale Calibration
A system full-scale calibration is performed after the bits
011 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 7). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The full-scale calibration will be per-
formed on the differential input voltage (2 REF
IN
/G)
present at the converter’s input over the next three conver-
sion periods (four in Slave Mode). When this is done, the
Operation Mode bits are reset to 000 (Normal Mode). A
single conversion is done with DRDY HIGH. After this
conversion, the DRDY signal goes LOW indicating resump-
tion of normal operation.
FIGURE 7. System Full-Scale Calibration Timing.
FIGURE 6. System Offset Calibration Timing.
Valid
Data
DRDY
Serial
I/O
Valid
Data
SC
(1)
t
DATA
Normal
Mode
Valid
Data
Valid
Data
Normal
Mode
Offset
Calibration on
Internal Offset
(2)
Self-Calibration
Mode
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
NOTES: (1) SC = Self-Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
Valid
Data
DRDY
Serial
I/O
Valid
Data
SFSC
(1)
t
DATA
Normal
Mode
Full-Scale
Calibration on
System Full-Scale
(2)
Analog
Input
Conversion
System Full-Scale
Calibration Mode
Possibly
Valid
Data
Possibly
Valid
Data
Normal
Mode
NOTES: (1) SFSC = System Full-Scale Calibration instruction.
(2) In Slave Mode, this function requires 4 cycles.
Self-Calibration
A self-calibration is performed after the bits 001 have been
written to the Command Register Operation Mode bits
(MD2 through MD0). This initiates the following sequence
at the start of the next conversion cycle (see Figure 5). The
DRDY signal will not go LOW but will remain HIGH and
will continue to remain HIGH throughout the calibration
sequence. The inputs to the sampling capacitor are discon-
nected from the converter’s analog inputs and are shorted
together. An offset calibration is performed over the next
three conversion periods (four in Slave Mode). Then, the
input to the sampling capacitor is connected across REF
IN
,
and a full-scale calibration is performed over the next three
conversions.
After this, the Operation Mode bits are reset to 000 (Normal
Mode) and the input capacitor is reconnected to the input.
Conversions proceed as usual over the next three cycles in
order to fill the digital filter. DRDY remains HIGH during
this time. On the start of the fourth cycle , DRDY goes LOW
indicating valid data and resumption of normal operation.
System Offset Calibration
A system offset calibration is performed after the bits 010
have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 6). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be per-
formed on the differential input voltage present at the
converter’s input over the next three conversion periods
(four in Slave Mode). When this is done, the Operation
相關(guān)PDF資料
PDF描述
ADS1286PA Analog-to-Digital Converter??? 12-Bit
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ADS1286PK Analog-to-Digital Converter??? 12-Bit
ADS1286PL Analog-to-Digital Converter??? 12-Bit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1286P 制造商:Texas Instruments 功能描述:IC 12BIT ADC 200 KHZ PDIP8 1286
ADS1286PA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KHz Unipol RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PA 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 1286 DIP8 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi
ADS1286PAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B Micro Pwr Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Micro Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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