參數(shù)資料
型號(hào)： ADS1286P
元件分類(lèi)： ADC
英文描述： Analog-to-Digital Converter??? 12-Bit
中文描述： 12位模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 15/42頁(yè)
文件大小： 872K
代理商： ADS1286P
ADS1212, 1213
SBAS064A
15
Normal operation returns within a single conversion cycle
because it is assumed that the input voltage at the converter’s
input is not removed immediately after the full-scale calibra-
tion is performed. In this case, the digital filter already
contains a valid result.
For full system calibration, offset calibration must be per-
formed first and then full-scale calibration. The calibration
error will be a sum of the rms noise on the conversion result
and the input signal noise. See the System Calibration Limits
section for information regarding the limits on the magni-
tude of the system full-scale voltage.
Pseudo System Calibration
The Pseudo System Calibration is performed after the bits
100 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
sequence (see Figure 8). At the start of the next conversion
cycle, the DRDY signal will not go LOW but will remain
HIGH and will continue to remain HIGH throughout the
calibration sequence. The offset calibration will be performed
on the differential input voltage present at the converter’s
input over the next three conversion periods (four in Slave
Mode). Then, the input to the sampling capacitor is discon-
nected from the converter’s analog input and connected
across REF
IN
. A gain calibration is performed over the next
three conversions.
After this, the Operation Mode bits are reset to 000 (Nor-
mal Mode) and the input capacitor is then reconnected to
the input. Conversions proceed as usual over the next three
cycles in order to fill the digital filter. DRDY remains
HIGH during this time. On the next cycle, the DRDY signal
goes LOW indicating valid data and resumption of normal
operation.
The system offset calibration range of the ADS1212/13
is limited and is listed in the Specifications Table. For
more information on how to use these specifications, see
the System Calibration Limits section. To calculate V
OS
,
use 2 REF
IN
/GAIN for V
FS
.
Background Calibration
The Background Calibration Mode is entered after the bits
101 have been written to the Command Register Operation
Mode bits (MD2 through MD0). This initiates the following
continuous sequence (see Figure 9). At the start of the next
conversion cycle, the DRDY signal will not go LOW but
will remain HIGH. The inputs to the sampling capacitor are
disconnected from the converter’s analog input and shorted
together. An offset calibration is performed over the next
three conversion periods (in Slave Mode, the very first offset
calibration requires four periods, and all subsequent offset
calibrations require three periods). Then, the input capacitor
is reconnected to the input. Conversions proceed as usual
over the next three cycles in order to fill the digital filter.
DRDY remains HIGH during this time. On the next cycle,
the DRDY signal goes LOW indicating valid data.
FIGURE 8. Pseudo System Calibration Timing.
FIGURE 9. Background Calibration Timing.
Valid
Data
DRDY
Serial
I/O
Valid
Data
PSC
(1)
t
DATA
Normal
Mode
Valid
Data
Valid
Data
Normal
Mode
Offset
Calibration on
System Offset
(2)
Pseudo System
Calibration Mode
Full-Scale
Calibration on
Internal Full-Scale
Analog
Input
Conversion
NOTES: (1) PSC = Pseudo System Calibration instruction. (2) In Slave Mode, this function requires 4 cycles.
Normal
Mode
Background Calibration
Mode
Valid
Data
DRDY
Serial
I/O
Valid
Data
BC
(1)
t
DATA
Offset
Calibration on
Internal Offset
(2)
Analog
Input
Conversion
Analog
Input
Conversion
Cycle Repeats
with Offset
Calibration
Full-Scale
Calibration on
Internal Full-Scale
NOTES: (1) BC = Background Calibration instruction. (2) In Slave Mode, the very first offset
calibration will require 4 cycles. All subsequent offset calibrations will require 3 cycles.
相關(guān)PDF資料
PDF描述
ADS1286PA Analog-to-Digital Converter??? 12-Bit
ADS1286PB Analog-to-Digital Converter??? 12-Bit
ADS1286PC Analog-to-Digital Converter??? 12-Bit
ADS1286PK Analog-to-Digital Converter??? 12-Bit
ADS1286PL Analog-to-Digital Converter??? 12-Bit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1286P 制造商:Texas Instruments 功能描述:IC 12BIT ADC 200 KHZ PDIP8 1286
ADS1286PA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KHz Unipol RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PA 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 1286 DIP8 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi
ADS1286PAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B Micro Pwr Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Micro Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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