參數(shù)資料
型號(hào)： ADS1286P
元件分類： ADC
英文描述： Analog-to-Digital Converter??? 12-Bit
中文描述： 12位模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 872K
代理商： ADS1286P
ADS1212, 1213
SBAS064A
20
DF (Data Format) Bit—
The DF bit controls the format of
the output data, either Two’s Complement or Offset Binary,
as follows:
DF
FORMAT
ANALOG INPUT
DIGITAL OUTPUT
0
Two
’
s
+Full-Scale
Zero
–
Full Scale
7FFFFF
H
000000
H
800000
H
Default
Complement
1
Offset Binary
+Full-Scale
Zero
–
Full-scale
FFFFFF
H
800000
H
000000
H
These two formats are the same for all bits except the most
significant, which is simply inverted in one format vs the
other. This bit only applies to the Data Output Register—it
has no effect on the other registers.
U/B (Unipolar) Bit—
The U/B bit controls the limits im-
posed on the output data, as follows:
U/B
MODE
LIMITS
0
1
Bipolar
Unipolar
None
Default
Zero to +Full-Scale only
The particular mode has no effect on the actual full-scale
range of the ADS1212/13, data format, or data format vs
input voltage. In the bipolar mode, the ADS1212/13 oper-
ates normally. In the unipolar mode, the conversion result is
limited to positive values only (zero included).
This bit only controls what is placed in the Data Output
Register. It has no effect on internal data. When cleared, the
very next conversion will produce a valid bipolar result.
BD (Byte Order) Bit—
The BD bit controls the order in
which bytes of data are read, either most significant byte
first or least significant byte, as follows:
SDL (Serial Data Line) Bit—
The SDL bit controls which
pin on the ADS1212/13 will be used as the serial data output
pin, either SDIO or SDOUT, as follows:
BD
BYTE ACCESS ORDER
0
Most Significant
to Least Significant Byte
Default
1
Least Significant
to Most Significant Byte
Note that when BD is clear and a multi-byte read is initiated,
A3-A0 of the Instruction Register is the address of the most
significant byte and subsequent bytes reside at higher ad-
dresses. If BD is set, then A3-A0 is the address of the least
significant byte and subsequent bytes reside at lower ad-
dresses. The BD bit only affects read operations, it has no
affect on write operations.
MSB (Bit Order) Bit—
The MSB bit controls the order in
which bits within a byte of data are read, either most
significant bit first or least significant bit, as follows:
MSB
BIT ORDER
0
1
Most Significant Bit First
Least Significant Bit First
Default
The MSB bit only affects read operations, it has no affect on
write operations.
SDL
SERIAL DATA OUTPUT PIN
0
1
SDIO
SDOUT
Default
If SDL is LOW, then SDIO will be used for both input and
output of serial data—see the Timing section for more
details on how the SDIO pin transitions between these two
states. In addition, SDOUT will remain in a tri-state condi-
tion at all times.
Important Note:
Since the default condition is SDL LOW,
SDIO has the potential of becoming an output once every
data output cycle if the ADS1212/13 is in the Master Mode.
This will occur until the Command Register can be written
and the SDL bit set HIGH. See the Interfacing section for
more information.
DRDY (Data Ready) Bit—
The DRDY bit is a read only bit
which reflects the state of the ADS1212/13’s DRDY output
pin, as follows:
DRDY
0
1
MEANING
Data Ready
Data Not Ready
DSYNC (Data Synchronization) Bit—
The DSYNC bit is
a write only bit which occupies the same location as DRDY.
When a ‘one’ is written to this location, the affect on the
ADS1212/13 is the same as if the DSYNC input pin had
been taken LOW and returned HIGH. That is, the modulator
count for the current conversion cycle will be reset to zero.
The DSYNC bit is provided in order to reduce the number of
interface signals that are needed between the ADS1212/13
and the main controller. Consult “Making Use of DSYNC”
in the Serial Interface section for more information.
MD2-MD0 (Operating Mode) Bits—
The MD2-MD0 bits
initiate or enable the various calibration sequences, as follows:
DSYNC
MEANING
0
1
No Change in Modulator Count
Modulator Count Reset to Zero
MD2
MD1
MD0
OPERATING MODE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Normal Mode
Self-Calibration
System Offset Calibration
System Full-Scale Calibration
Pseudo System Calibration
Background Calibration
Sleep
Reserved
The Normal Mode, Background Calibration Mode, and
Sleep Mode are permanent modes and the ADS1212/13 will
remain in these modes indefinitely. All other modes are
temporary and will revert to Normal Mode once the appro-
priate actions are complete. See the Calibration and Sleep
Mode sections for more information.
相關(guān)PDF資料
PDF描述
ADS1286PA Analog-to-Digital Converter??? 12-Bit
ADS1286PB Analog-to-Digital Converter??? 12-Bit
ADS1286PC Analog-to-Digital Converter??? 12-Bit
ADS1286PK Analog-to-Digital Converter??? 12-Bit
ADS1286PL Analog-to-Digital Converter??? 12-Bit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1286P 制造商:Texas Instruments 功能描述:IC 12BIT ADC 200 KHZ PDIP8 1286
ADS1286PA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KHz Unipol RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PA 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 1286 DIP8 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi
ADS1286PAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B Micro Pwr Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Micro Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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