參數(shù)資料
型號： ADS1286P
元件分類： ADC
英文描述： Analog-to-Digital Converter??? 12-Bit
中文描述： 12位模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 19/42頁
文件大?。?/td> 872K
代理商： ADS1286P
ADS1212, 1213
SBAS064A
19
The Command Register (CMR) controls all of the ADS1212/
13’s options and operating modes. These include the PGA
gain setting, the Turbo Mode Rate, the output data rate
(decimation ratio), etc. The CMR is the only 32-bit register
within the ADS1212/13. It, and all the remaining registers,
may be read from or written to.
Instruction Register (INSR)
The INSR is an 8-bit register which commands the serial
interface either to read or to write “n” bytes beginning at the
specified register location. Table VIII shows the format for
the INSR.
Each serial communication starts with the 8-bits of the INSR
being sent to the ADS1212/13. This directs the remainder of
the communication cycle, which consists of n bytes being
read from or written to the ADS1212/13. The read/write bit,
the number of bytes n, and the starting register address are
defined, as shown in Table VIII. When the n bytes have been
transferred, the INSR is complete. A new communication
cycle is initiated by sending a new INSR (under restrictions
outlined in the Interfacing section).
Command Register (CMR)
The CMR controls all of the functionality of the ADS1212/
13. The new configuration takes effect on the negative
transition of SCLK for the last bit in each byte of data being
written to the command register. The organization of the
CMR is shown in Table X.
The internal reference circuitry consumes approximately
1.6mA of steady state current with no external load. See the
Reference Output section for full details on the internal
reference.
TABLE VIII. Instruction Register.
R/W (Read/Write) Bit—
For a write operation to occur, this
bit of the INSR must be 0. For a read, this bit must be 1, as
follows:
MB1, MB0 (Multiple Bytes) Bits—
These two bits are used
to control the word length (number of bytes) of the read or
write operation, as follows:
A3-A0 (Address) Bits—
These four bits select the begin-
ning register location which will be read from or written to,
as shown in Table IX. Each subsequent byte will be read
from or written to the next higher location. (If the BD bit in
the Command Register is set, each subsequent byte will be
read from the next lower location. This bit does not affect the
write operation.) If the next location is not defined in Table
IX, then the results are unknown. Reading or writing contin-
ues until the number of bytes specified by MB1 and MB0
have been transferred.
A3
A2
A1
A0
REGISTER BYTE
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
0
1
0
1
0
1
0
0
1
0
Data Output Register Byte 2 (MSB)
Data Output Register Byte 1
Data Output Register Byte 0 (LSB)
Command Register Byte 3 (MSB)
Command Register Byte 2
Command Register Byte 1
Command Register Byte 0 (LSB)
Offset Cal Register Byte 2 (MSB)
Offset Cal Register Byte 1
Offset Cal Register Byte 0 (LSB)
Full-Scale Cal Register Byte 2 (MSB)
Full-Scale Cal Register Byte 1
Full-Scale Cal Register Byte 0 (LSB)
Note: MSB = Most Significant Byte, LSB = Least Significant Byte
R/W
0
1
Write
Read
MB1
0
0
1
1
MB0
0
1
0
1
1 Byte
2 Bytes
3 Bytes
4 Bytes
TABLE IX. A3-A0 Addressing.
MSB
LSB
R/W
MB1
MB0
0
A3
A2
A1
A0
The V
BIAS
circuitry consumes approximately 1mA of steady
state current with no external load. See the V
BIAS
section for
full details. When the internal reference (REF
OUT
) is con-
nected to the reference input (REF
IN
), V
BIAS
is 3.3V, nominal.
REFO (Reference Output) Bit—
The REFO bit controls
the internal reference (REF
OUT
) state, either on (2.5V) or off
(disabled), as follows:
REFO
INTERNAL REFERENCE
REF
OUT
STATUS
0
1
Off
On
High Impedance
2.5V
Default
BIAS (Bias Voltage) Bit—
The BIAS bit controls the V
BIAS
output state—either on (1.33 REF
IN
) or off (disabled), as
follows:
BIAS
V
BIAS
GENERATOR
Off
On
V
BIAS
STATUS
Disabled
1.33
REF
IN
0
1
Default
Most Significant Bit
Byte 3
DSYNC
(1)
DRDY
BIAS
REFO
DF
U/B
BD
MSB
SDL
0 Off
1 On
0 Two
’
s 0 Biplr 0 MSByte 0 MSB 0 SDIO
0
Defaults
NOTE: (1) DSYNC is Write only, DRDY is Read only.
Byte 2
MD2
MD1
MD0
G2
G1
G0
CH1
CH0
000 Normal Mode
000 Gain 1
00 Channel 1
Defaults
Byte 1
SF2
SF1
SF0
DR12
DR11
DR10
DR9
DR8
000 Turbo Mode Rate of 1
00000
Defaults
Byte 0
Least Significant Bit
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
(00000) 0001 0111 (23) Data Rate of 326Hz
Defaults
TABLE X. Organization of the Command Register and
Default Status.
相關(guān)PDF資料
PDF描述
ADS1286PA Analog-to-Digital Converter??? 12-Bit
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ADS1286PC Analog-to-Digital Converter??? 12-Bit
ADS1286PK Analog-to-Digital Converter??? 12-Bit
ADS1286PL Analog-to-Digital Converter??? 12-Bit
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADS1286P 制造商:Texas Instruments 功能描述:IC 12BIT ADC 200 KHZ PDIP8 1286
ADS1286PA 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12bit 200KHz Unipol RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PA 制造商:BURR-BROWN 功能描述:IC 12BIT ADC 1286 DIP8 制造商:Texas Instruments 功能描述:Analog-Digital Converter IC Number of Bi
ADS1286PAG4 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12B Micro Pwr Sampling ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
ADS1286PB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit Micro Power Sampling RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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