參數(shù)資料
型號: ADF4360-9BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 5/24頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER W/ADJ VCO 24LFCSP
標準包裝: 1
類型: 扇出配送,整數(shù)-N,合成器(RF)
PLL:
輸入: CMOS
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 400MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標準包裝
產(chǎn)品目錄頁面: 551 (CN2011-ZH PDF)
其它名稱: ADF4360-9BCPZRL7DKR
Data Sheet
ADF4360-9
Rev. C | Page 13 of 24
LATCH STRUCTURE
Figure 22 shows the three on-chip latches for the ADF4360-9. The two LSBs decide which latch is programmed.
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
PC1
PC2
CR
D1
D2
PDP
CP
CPG
MTLD
PL1
PL2
CPI1
CPI2
CPI3
CPI4
CPI5
CPI6
PD1
D3
CONTROL
BITS
DIVOUT
CONTROL
CURRENT
SETTING 2
CURRENT
SETTING 1
CORE
POWER
LEVEL
OUTPUT
POWER
LEVEL
CONTROL LATCH
DB21
DB22
DB23
PO
W
ER
-
DO
W
N
2
PO
W
ER
-
DO
W
N
1
CO
UNT
E
R
ESET
M
U
TE
-TILL-
LD
R
ESER
VED
R
ESER
VED
CP
G
AI
N
CP
T
HRE
E
-
S
TA
TE
P
HAS
E
D
E
TE
C
TOR
P
OLA
R
ITY
PD2
RSV
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (1) C1 (0)
A1
A2
A3
A4
A5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
RSV
CONTROL
BITS
5-BIT DIVOUT
13-BIT B COUNTER
N COUNTER LATCH
DB21
DB22
DB23
CP
G
AI
N
R
ESER
VED
R
ESER
VED
R
ESER
VED
CPG
RSV
DB20
DB19
DB18
DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
ANTI-
BACKLASH
PULSE WIDTH
14-BIT REFERENCE COUNTER
BAND
SELECT
CLOCK
R COUNTER LATCH
DB21
DB22
DB23
R
ESER
VED
R
ESER
VED
T
EST
MO
D
E
BI
T
LOC
K
DE
T
E
CT
PR
EC
ISI
O
N
BSC2
RSV
07139-
034
Figure 22. Latch Structure
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