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參數(shù)資料
| 型號： | ADF4360-9BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 其它名稱： | ADF4360-9BCPZRL7DKR |
ADF4360-9
Data Sheet
Rev. C | Page 20 of 24
APPLICATIONS
CHOOSING THE CORRECT INDUCTANCE VALUE
The ADF4360-9 can be used at many different frequencies
simply by choosing the external inductors to give the correct
output frequency. Figure 27 shows a graph of both minimum
and maximum frequency vs. the external inductor value. The
correct inductor should cover the maximum and minimum
frequencies desired. The inductors used are 0603 CS or 0805 CS
type from Coilcraft. To reduce mutual coupling, the inductors
should be placed at right angles to one another.
The lowest center frequency of oscillation possible is approximately
65 MHz, which is achieved using 560 nH inductors. This
relationship can be expressed by
(
)
EXT
O
L
f
+
=
nH
0.9
pF
9.3
2π
1
where:
fO is the center frequency.
LEXT is the external inductance.
0
150
50
100
350
250
300
200
450
400
0
100
200
300
400
600
500
INDUCTANCE (nH)
F
RE
Q
UE
NC
Y
(MH
z)
07139
-025
Figure 27. Output Center Frequency vs. External Inductor Value
The approximate value of capacitance at the midpoint of the
center band of the VCO is 9.3 pF, and the approximate value of
internal inductance due to the bond wires is 0.9 nH. The VCO
sensitivity is a measure of the frequency change vs. the tuning
voltage. It is a very important parameter for the low-pass filter.
Figure 28 shows a graph of the tuning sensitivity (in MHz/V)
vs. the inductance (nH). It can be seen that as the inductance
increases, the sensitivity decreases. This relationship can be
derived from the previous equation; that is, because the
inductance increased, the change in capacitance from the
varactor has less of an effect on the frequency.
0
4
2
10
8
6
12
0
100
200
300
400
600
500
INDUCTANCE (nH)
SEN
SI
T
IVI
T
Y
(MH
z/
V)
07139-
026
Figure 28. Tuning Sensitivity vs. Inductance
ENCODE CLOCK FOR ADC
Analog-to-digital converters (ADCs) require a sampling clock
for their operation. Generally, this is provided by TCXO or VCXOs,
which can be large and expensive. The frequency range is usually
quite limited. An alternative solution is the ADF4360-9, which can
be used to generate a CMOS clock signal suitable for use in all
but the most demanding converter applications.
Figure 29 shows an ADF4360-9 with a VCO frequency of
320 MHz and a DIVOUT frequency of 80 MHz. Because a 50%
duty cycle is preferred by most sampling clock circuitry, the A/2
mode is selected. Therefore, A is programmed to 2, giving an
overall divide value of 4. The AD9215-80 is a 10-bit, 80 MSPS
ADC that requires an encode clock jitter of 6 ps or less. The
ADF4360-9 takes a 10 MHz TCXO frequency and divides this to
1 MHz; therefore, R = 10 is programmed and N = 320 is
programmed
to achieve a VCO frequency of 320 MHz. The resultant 80 MHz
CMOS signal has a jitter of <1.5 ps, which is more than adequate
for the application.
TCXO
10MHz
ADF4360-9
80MHz
470
21nH
LPF
SIGNAL
GENERATOR
HC-ADC-
EVALA-SC
USB
SPI
PC
ENCODE
CLOCK
AD9215-80
AIN
07139-
036
Figure 29. The ADF4360-9 Used as an Encode Clock for an ADC
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