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參數(shù)資料
| 型號(hào)： | ADF4360-9BCPZRL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 1/24頁(yè) |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER W/ADJ VCO 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無(wú)/無(wú) |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 是/無(wú) |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 551 (CN2011-ZH PDF) |
| 其它名稱： | ADF4360-9BCPZRL7DKR |
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Clock Generator PLL with Integrated VCO
Data Sheet
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
2008–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Primary output frequency range: 65 MHz to 400 MHz
Auxiliary divider from 2 to 31, output from 1.1 MHz to 200 MHz
3.0 V to 3.6 V power supply
1.8 V logic compatibility
Integer-N synthesizer
Programmable output power level
3-wire serial interface
Digital lock detect
Software power-down mode
APPLICATIONS
System clock generation
Test equipment
Wireless LANs
CATV equipment
GENERAL DESCRIPTION
The ADF4360-9 is an integrated integer-N synthesizer and
voltage-controlled oscillator (VCO). External inductors set the
ADF4360-9 center frequency. This allows a VCO frequency
range of between 65 MHz and 400 MHz.
An additional divider stage allows division of the VCO signal.
The CMOS level output is equivalent to the VCO signal divided
by the integer value between 2 and 31. This divided signal can
be further divided by 2, if desired.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
14-BIT R
COUNTER
AVDD
CLK
DATA
VTUNE
CN
CC
RFOUTA
RFOUTB
LD
CP
VVCO
L1
DIVOUT
L2
LE
DVDD
RSET
LOCK
DETECT
MULTIPLEXER
MUTE
CHARGE
PUMP
PHASE
COMPARATOR
24-BIT DATA
REGISTER
ADF4360-9
13-BIT B
COUNTER
N = B
VCO
CORE
DIVIDE-BY-A
(2 TO 31)
DIVIDE-BY-2
OUTPUT
STAGE
24-BIT
FUNCTION
LATCH
REFIN
AGND
DGND
CPGND
07139-
001
Figure 1.
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