AVDD = DV
參數(shù)資料
型號: ADF4360-9BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER W/ADJ VCO 24LFCSP
標準包裝: 1
類型: 扇出配送,整數(shù)-N,合成器(RF)
PLL:
輸入: CMOS
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 400MHz
除法器/乘法器: 是/無
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 24-LFCSP-VQ(4x4)
包裝: 標準包裝
產(chǎn)品目錄頁面: 551 (CN2011-ZH PDF)
其它名稱: ADF4360-9BCPZRL7DKR
Data Sheet
ADF4360-9
Rev. C | Page 5 of 24
TIMING CHARACTERISTICS1
AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
t1
20
ns min
LE setup time
t2
10
ns min
DATA to CLK setup time
t3
10
ns min
DATA to CLK hold time
t4
25
ns min
CLK high duration
t5
25
ns min
CLK low duration
t6
10
ns min
CLK to LE setup time
t7
20
ns min
LE pulse width
1
Refer to the Power-Up section for the recommended power-up procedure for this device.
CLK
DATA
LE
DB23 (MSB)
DB22
DB2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t1
t2
t3
t7
t6
t4
t5
07139-
002
Figure 2. Timing Diagram
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