參數(shù)資料
型號(hào)： ADE7753ARSZRL
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO20
封裝： ROHS COMPLIANT, MO-150AE, SSOP-20
文件頁(yè)數(shù)： 30/60頁(yè)
文件大小： 938K
代理商： ADE7753ARSZRL
ADE7753
Rev. C | Page 36 of 60
compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement is
done by calibrating each individual rms measurement.
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent
power.
∫
=
dt
t
Power
Apparent
Energy
Apparent
)
(
(30)
The ADE7753 achieves the integration of the apparent power
signal by continuously accumulating the apparent power signal
in an internal 49-bit register. The apparent energy register
(VAENERGY[23:0]) represents the upper 24 bits of this internal
register. This discrete time accumulation or summation is
equivalent to integration in continuous time. Equation 31
expresses the relationship
×
=
∑
∞
=
→
0
)
(
n
T
nT
Power
Apparent
Lim
Energy
Apparent
(31)
where:
n is the discrete time sample number.
T is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7753 is 1.1 μs (4/CLKIN).
Figure 75 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy remains theoretically always positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, then the internal active energy
register is divided by 1. VADIV is an 8-bit unsigned register.
The upper 24 bits are then written in the 24-bit apparent energy
register (VAENERGY[23:0]). RVAENERGY register (24 bits
long) is provided to read the apparent energy. This register is
reset to 0 after a read operation.
Figure 76 shows this apparent energy accumulation for full-scale
signals (sinusoidal) on the analog inputs. The three curves
displayed illustrate the minimum time it takes the energy register
to roll over when the VAGAIN registers content is equal to 0x7FF,
0x000, and 0x800. The VAGAIN register is used to carry out an
apparent power calibration in the ADE7753. As shown, the fastest
integration time occurs when the VAGAIN register is set to
maximum full scale, i.e., 0x7FF.
VADIV
APPARENT POWER
+
VAENERGY [23:0]
APPARENT POWER ARE
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER
23
0
48
0
48
0
02875-0-074
%
TIME (nT)
T
ACTIVE POWER
SIGNAL = P
Figure 75. ADE7753 Apparent Energy Calculation
0xFF,FFFF
0x80,0000
0x40,0000
0x20,0000
0x00,0000
VAENERGY[23:0]
6.26
12.52
18.78
25.04
TIME (minutes)
VAGAIN = 0x7FF
VAGAIN = 0x000
VAGAIN = 0x800
02875-0-075
Figure 76. Energy Register Rollover Time for Full-Scale Power
(Maximum and Minimum Power Gain)
Note that the apparent energy register is unsigned—see Figure 76.
By using the interrupt enable register, the ADE7753 can be con-
figured to issue an interrupt (IRQ) when the apparent energy
register is more than half full or when an overflow occurs. The
half full interrupt for the unsigned apparent energy register is
based on 24 bits as opposed to 23 bits for the signed active energy
register.
Integration Times under Steady Load
As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1 μs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 0x000, the average word value from
apparent power stage is 0xAD055—see the Apparent Power
Calculation section. The maximum value that can be stored in
the apparent energy register before it overflows is 224 or
0xFF,FFFF. The average word value is added to the internal
register, which can store 248 or 0xFFFF,FFFF,FFFF before it
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