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參數(shù)資料
| 型號： | ADE7753ARSZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | ROHS COMPLIANT, MO-150AE, SSOP-20 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大?。?/td> | 938K |
| 代理商： | ADE7753ARSZRL |
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ADE7753
Rev. C | Page 21 of 60
Using the ADE7753 Interrupts with an MCU
ADE7753 INTERRUPTS
Figure 46 shows a timing diagram with a suggested implemen-
tation of ADE7753 interrupt management using an MCU. At
time t1, the IRQ line goes active low indicating that one or more
interrupt events have occurred in the ADE7753. The IRQ logic
output should be tied to a negative edge-triggered external
interrupt on the MCU. On detection of the negative edge, the
MCU should be configured to start executing its interrupt
service routine (ISR). On entering the ISR, all interrupts should
be disabled by using the global interrupt enable bit. At this
point, the MCU external interrupt flag can be cleared to capture
interrupt events that occur during the current ISR. When the
MCU interrupt flag is cleared, a read from the status register
with reset is carried out. This causes the IRQ line to be reset
logic high (t2)—see the
section. The status
register contents are used to determine the source of the
interrupt(s) and therefore the appropriate action to be taken. If
a subsequent interrupt event occurs during the ISR, that event is
recorded by the MCU external interrupt flag being set again
(t3). On returning from the ISR, the global interrupt mask is
cleared (same instruction cycle), and the external interrupt flag
causes the MCU to jump to its ISR once a gain. This ensures
that the MCU does not miss any external interrupts.
ADE7753 interrupts are managed through the interrupt status
register (STATUS[15:0]) and the interrupt enable register
(IRQEN[15:0]). When an interrupt event occurs in the ADE7753,
the corresponding flag in the status register is set to Logic 1—
see the Interrupt Status Register section. If the enable bit for this
interrupt in the interrupt enable register is Logic 1, then the
IRQ logic output goes active low. The flag bits in the status
register are set irrespective of the state of the enable bits.
To determine the source of the interrupt, the system master
(MCU) should perform a read from the status register with
reset (RSTSTATUS[15:0]). This is achieved by carrying out a
read from Address 0x0C. The IRQ output goes logic high on
completion of the interrupt status register read command—see
the
section. When carrying out a read with
reset, the ADE7753 is designed to ensure that no interrupt
events are missed. If an interrupt event occurs just as the status
register is being read, the event is not lost and the
IRQ logic
output is guaranteed to go high for the duration of the interrupt
status register data transfer before going logic low again to
indicate the pending interrupt. See the next section for a more
detailed description.
IRQ
GLOBAL
INTERRUPT
MASK SET
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
CLEAR MCU
INTERRUPT
FLAG
READ
STATUS WITH
RESET (0x05)
ISR ACTION
(BASED ON STATUS CONTENTS)
MCU
INTERRUPT
FLAG SET
MCU
PROGRAM
SEQUENCE
02875-0-044
t1
t2
t3
JUMP
TO
ISR
JUMP
TO
ISR
Figure 45. ADE7753 Interrupt Management
SCLK
DIN
DOUT
IRQ
t11
t9
t1
READ STATUS REGISTER COMMAND
STATUS REGISTER CONTENTS
DB7
DB0
CS
00
0
01
0
1
DB0
02875-0-045
Figure 46. ADE7753 Interrupt Timing
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