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| 型號： | AD9992BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/92頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 托盤 |
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AD9992
Rev. C | Page 39 of 92
Complete Field: Combining V-Sequences
After the V-sequences are created, they are combined to create
different readout fields. A field consists of up to nine regions,
and within each region, a different V-sequence can be selected.
Figure 48 shows how the sequence change positions (SCP)
designate the line boundary for each region and how the SEQ
registers then select which V-sequence is used in each region.
Registers to control the VSG outputs are also included in the field
registers. Table 17 summarizes the registers used to create the
fields.
The SEQ registers, one for each region, select which V-sequences
are active in each region. The MULT_SWEEP registers, one for
each region, are used to enable sweep mode and/or multiplier
mode in any region. The SCP registers create the line boundaries
for each region. The VDLEN register specifies the total number of
lines in the field. The HDLEN register specifies the total number of
pixels per line, and the HDLASTLEN register specifies the
number of pixels in the last line of the field.
The VPATSECOND register is used to add a second V-pattern
group to the XV1 to XV10 outputs in the vertical sensor gate
(VSG) line. The SGMASK register is used to enable or disable each
individual VSG output. There are two bits for each VSG output
to enable separate masking in SGACTLINE1 and SGACTLINE2.
Setting a masking bit high masks the output; setting it low enables
the output. The VSGPATSEL register assigns one of the eight
SG patterns to each VSG output. Individual SG patterns are created
separately using the SG pattern registers. The SGACTLINE1
register specifies which line in the field contains the VSG outputs.
The optional SGACTLINE2 register allows the same VSG pulses to
be repeated on a different line. Separate masking is not available
for SGACTLINE1 and SGACTLINE2.
Table 17. Field Registers (CLPOB, PBLK Masking Shown in Table 10)
Register
Length
Range
Description
SEQx
5b
0 to 31 V-sequence number
Selected V-sequence for each region in the field.
MULT_SWEEP
2b
0 to 3
Enables multiplier mode and/or sweep mode for each region.
0: Multiplier off, sweep off.
1: Multiplier off, sweep on.
2: Multiplier on, sweep off.
3: Multiplier on, sweep on.
SCP
13b
0 to 8191 line number
Sequence change position for each region.
VDLEN
13b
0 to 8191 lines
Total number of lines in each field.
HDLASTLEN
13b
0 to 8191 pixels
Length in pixels of the last HD line in each field.
VSGPATSEL
24b
High/low
VSGPATSEL selects which V-pattern toggle positions are used. When set to 0,
Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used.
[0]: XV1 selection (0 = use XVTOG1, XVTOG2; 1 = use XVTOG3, XVTOG4).
…
[23]: XV24 selection.
SGMASK
24b
High/low, each VSG
Set high to mask each individual VSG output.
[0]: XV1 mask.
…
[23]: XV24 mask.
SGACTLINE1
13b
0 to 8191 line number
Selects the line in the field where the VSG signals are active.
SGACTLINE2
13b
0 to 8191 line number
Selects a second line in the field to repeat the VSG signals. If not used,
set this equal to SGACTLINE1 or to the maximum value.
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| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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