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| 型號(hào)： | AD9992BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/92頁(yè) |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 托盤 |
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AD9992
Rev. C | Page 28 of 92
Vertical Pattern Groups (VPAT)
The vertical pattern groups define the individual pulse patterns for
each XV1 to XV24 output signal. Table 13 summarizes the registers
available for generating each of the V-pattern groups. The first,
second, third, and fourth toggle positions (XVTOG1, XVTOG2,
XVTOG3, and XVTOG4) are the pixel locations within the line
where the pulse transitions. All toggle positions are 13-bit values,
allowing their placement anywhere in the horizontal line.
More registers are included in the vertical sequence registers to
specify the output pulses. VPOL specifies the start polarity for
each signal; VSTART specifies the start position of the V-pattern
group within the line; VLEN designates the total length of
the V-pattern group, which determines the number of pixels
between each of the pattern repetitions when repetitions are used.
The VSTART position is actually an offset value for each toggle
position. The actual pixel location for each toggle, measured
from the HD falling edge (Pixel 0), is equal to the VSTART value
plus the toggle position.
When the selected V-output is designated as a VSG pulse, either
the XVTOG1/XVTOG2 or XVTOG3/XVTOG4 pair is selected
using V-Sequence Address 0x02, VSGPATSEL. All four toggle
positions are not simultaneously available for VSG pulses.
Unused V-channels must have their toggle positions programmed
to either 0 or maximum value. This prevents unpredictable
behavior because the default values of the V-pattern group registers
are unknown.
Table 13. Vertical Pattern Group Registers
Register
Length
Description
XVTOG1
13b
First toggle position within line for each XV1 to XV24 output, relative to VSTART value.
XVTOG2
13b
Second toggle position, relative to VSTART value
XVTOG3
13b
Third toggle position, relative to VSTART value
XVTOG4
13b
Fourth toggle position, relative to VSTART value
4
1
2
3
1
23
1
2
3
START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS.
PROGRAMMABLE SETTINGS:
1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS).
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS).
4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS).
05
89
1-
03
4
XV1
HD
XV2
XV24
Figure 34. Vertical Pattern Group Programmability
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| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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