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| 型號(hào)： | AD9992BBCZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/92頁 |
| 文件大小： | 0K |
| 描述： | IC CCD SGNL PROC 12BIT 105CSPBGA |
| 產(chǎn)品變化通告： | AD9992 Discontinuation 22/Feb/2012 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號(hào)處理器，12 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 27mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 105-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 105-CSPBGA（8x8） |
| 包裝： | 托盤 |
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AD9992
Rev. C | Page 19 of 92
HORIZONTAL CLAMPING AND BLANKING
The horizontal clamping and blanking pulses of the AD9992
are fully programmable to suit a variety of applications.
Individual control is provided for CLPOB, PBLK, and HBLK in
the different regions of each field. This allows the dark pixel
clamping and blanking patterns to be changed at each stage of
the readout to accommodate different image transfer timing
and high speed line shifts.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 22. These two signals are programmed
independently using the registers listed in Table 10. The start
polarity for the CLPOB (and PBLK) signal is CLPOBPOL
(PBLKPOL), and the first and second toggle positions of the pulse
are CLPOBTOG1 (PBLKTOG1) and CLPOBTOG2 (PBLKTOG2).
Both signals are active low and should be programmed
accordingly.
A separate pattern for CLPOB and PBLK can be programmed
for each vertical sequence. As described in the Vertical Timing
Generation section, several V-sequences can be created, each
containing a unique pulse pattern for CLPOB and PBLK. Figure 48
shows how the sequence change positions divide the readout field
into different regions. By assigning a different V-sequence to
each region, the CLPOB and PBLK signals can change with
each change in the vertical timing.
CLPOB and PBLK Masking Areas
Additionally, the AD9992 allows the CLPOB and PBLK signals to
be disabled in certain lines in the field without changing any of
the existing CLPOB pattern settings.
To use CLPOB (or PBLK) masking, the CLPMASKSTART
(PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND)
registers are programmed to specify the start and end lines in
the field where the CLPOB (PBLK) patterns are ignored. The three
sets of start and end registers allow up to three CLPOB (PBLK)
masking areas to be created.
The CLPOB and PBLK masking registers are not specific to
a certain V-sequence; they are always active for any existing field of
timing. During operation, to disable the CLPOB masking
feature, these registers must be set to the maximum value of
0x1FFF or a value greater than the programmed VD length.
Note that to disable CLPOB (and PBLK) masking during power-up,
it is recommended to set CLPMASKSTART (PBLKMASKSTART)
to 8191 and CLPMASKEND (PBLKMASKEND) to 0. This
prevents any accidental masking caused by register update events.
Table 10. CLPOB and PBLK Pattern Registers
Register
Length
Range
Description
CLPOBPOL
1b
High/low
Starting polarity of CLPOB for each V-sequence.
PBLKPOL
1b
High/low
Starting polarity of PBLK for each V-sequence.
CLPOBTOG1
13b
0 to 8191 pixel locations
First CLPOB toggle position within line for each V-sequence.
CLPOBTOG2
13b
0 to 8191 pixel locations
Second CLPOB toggle position within line for each V-sequence.
PBLKTOG1
13b
0 to 8191 pixel locations
First PBLK toggle position within line for each V-sequence.
PBLKTOG2
13b
0 to 8191 pixel locations
Second PBLK toggle position within line for each V-sequence.
CLPMASKSTART
13b
0 to 8191 line locations
CLPOB masking area—starting line within field (maximum of three areas).
CLPMASKEND
13b
0 to 8191 line locations
CLPOB masking area—ending line within field (maximum of three areas).
PBLKMASKSTART
13b
0 to 8191 line locations
PBLK masking area—starting line within field (maximum of three areas).
PBLKMASKEND
13b
0 to 8191 line locations
PBLK masking area—ending line within field (maximum of three areas).
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| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測(cè)器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應(yīng)商器件封裝:196-CSPBGA（12x12） 標(biāo)準(zhǔn)包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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