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參數(shù)資料
| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–16–
VERTICAL TIMING GENERATION
The AD9991 provides a very exible solution for generating
vertical CCD timing, and can support multiple CCDs and dif-
ferent system architectures. The 6-phase vertical transfer clocks
V1–V6 are used to shift each line of pixels into the horizontal
output register of the CCD. The AD9991 allows these outputs to
be individually programmed into various readout congurations
using a four step process.
Figure 15 shows an overview of how the vertical timing is gener-
ated in four steps. First, the individual pulse patterns for V1–V6
are created by using the vertical pattern group registers. Second,
the V-pattern groups are used to build the sequences, where
additional information is added. Third, the readout for an entire
eld is constructed by dividing the eld into different regions and
then assigning a sequence to each region. Each eld can contain
up to seven different regions to accommodate different steps of
the readout such as high speed line shifts and unique vertical line
transfers. Up to six different elds may be created. Finally, the
Mode register allows the different elds to be combined into any
order for various readout congurations.
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 3
REGION 1: USE V-SEQUENCE 2
REGION 2: USE V-SEQUENCE 1
REGION 0: USE V-SEQUENCE 2
REGION 1: USE V-SEQUENCE 0
REGION 3: USE V-SEQUENCE 0
REGION 4: USE V-SEQUENCE 2
CREATE THE VERTICAL PATTERN GROUPS
(MAXIMUM OF 10 GROUPS).
BUILD THE V-SEQUENCES BY ADDING LINE START
POSITION, # OF REPEATS, AND HBLK/CLPOB PULSES
(MAXIMUM OF 10 V-SEQUENCES).
V-SEQUENCE 0
(VPAT0, 1 REP)
BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS,
AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH
(MAXIMUM OF 7 REGIONS IN EACH FIELD)
(MAXIMUM OF 6 FIELDS).
V1
V2
V5
V6
V1
V2
V3
V4
FIELD 0
FIELD 1
FIELD 2
REGION 2: USE V-SEQUENCE 3
USE THE MODE REGISTER TO CONTROL WHICH FIELDS
ARE USED, AND IN WHAT ORDER
(MAXIMUM OF 7 FIELDS MAY BE COMBINED IN ANY ORDER).
FIELD 0
FIELD 1
FIELD 2
FIELD 3
FIELD 4
FIELD 5
FIELD 1
FIELD 4
FIELD 2
V4
V3
V5
V6
V-SEQUENCE 1
(VPAT9, 2 REP)
V-SEQUENCE 2
(VPAT9, N REP)
VPAT 0
V1
V2
V5
V6
V4
V3
V1
V2
V5
V6
V4
V3
V1
V2
V5
V6
V4
V3
VPAT 9
Figure 15. Summary of Vertical Timing Generation
REV. 0
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