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| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
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AD9991
–39–
Updating of New Register Values
The AD9991’s internal registers are updated at different times,
depending on the particular register. Table XV summarizes the
four different types of register updates:
1. SCK Updated: Some of the registers in Bank 1 are updated
immediately, as soon as the 24th data bit (D23) is written.
These registers are used for functions that do not require
gating with the next VD boundry, such as power-up and reset
functions. These registers are lightly shaded in gray in the
Bank 1 register list.
The Bank Select register (addr 0x7F in Bank 1 and 2) is also
SCK updated.
2. VD Updated: Most of the registers in Bank 1, as well as
the Field registers in Bank 2, are updated at the next VD
falling edge. By updating these values at the next VD edge,
the current eld will not be corrupted and the new register
values will be applied to the next eld. The Bank 1 register
updates may be further delayed past the VD falling edge
by using the UPDATE register (addr 0x19). This will delay
the VD updated register updates to any HD line in the eld.
Note that the Bank 2 registers are not affected by the UPDATE
register.
3. SG-Line Updated: A few of the registers in Bank 1 are
updated at the end of the SG active line, at the HD falling
edge. These are the registers to control the SUBCK signal
so that the SUBCK output will not be updated until after
the SG line has been completed. These registers are darkly
shaded in gray in the Bank 1 register list.
4. SCP Updated: In Bank 2, all of the V-pattern group and
V-sequence registers (addr 0x00 through 0xCF, exclud-
ing 0x7F) are updated at the next SCP, where they will
be used. For example, in Figure 42, this eld has selected
Region 1 to use V-Sequence 3 for the vertical outputs.
This means that a write to any of the V-Sequence 3 reg-
isters, or any of the V-pattern group registers that are
referenced by V-Sequence 3 will be updated at SCP1. If
multiple writes are done to the same register, the last one
done before SCP1 will be the one that is updated. Likewise,
register writes to any V-Sequence 5 registers will be updated
at SCP2, and register writes to any V-Sequence 8 registers
will be updated at SCP3.
Table XV. Register Update Locations
Update Type
Register Bank
Description
SCK Updated
Bank 1 Only
Register is immediately updated when the 24th data bit (D23) is clocked in.
VD Updated
Bank 1 and Bank 2
Register is updated at the VD falling edge. VD updated registers in Bank 1 may be
delayed further by using the UPDATE register at address 0x19 in Bank 1. Bank 2
updates will not be affected by the UPDATE register.
SG Line Updated
Bank 1 Only
Register is updated at the HD falling edge at the end of the SG-active line.
SCP Updated
Bank 2 Only
Register is updated at the next SCP when the register will be used.
VD
REGION 0
HD
SCP 1
SCP 2
SCP 3
REGION 1
REGION 2
REGION 3
VSG
SGLINE
SCP 0
SERIAL
WRITE
SCK
UPDATED
SCP 0
VD
UPDATED
SG
UPDATED
SCP
UPDATED
V1–V6
USE VSEQ2
USE VSEQ3
USE VSEQ5
USE VSEQ8
Figure 42. Register Update Locations (See Table XV for Denitions)
REV. 0
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