- 您現在的位置：買賣IC網 > PDF目錄1895 > AD9991KCPZRL (Analog Devices Inc)IC CCD SIGNAL PROCESSOR 56-LFCSP PDF資料下載
參數資料
| 型號： | AD9991KCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 14/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| 產品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標準包裝： | 2,500 |
| 類型： | CCD 信號處理器，10 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁當前第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁
AD9991
–21–
Sweep Mode Operation
The AD9991 contains an additional mode of vertical timing
operation called Sweep mode. This mode is used to generate a
large number of repetitive pulses that span multiple HD lines.
One example of where this mode is needed is at the start of the
CCD readout operation. At the end of the image exposure but
before the image is transferred by the sensor gate pulses, the
vertical interline CCD registers should be free of all charge. This
can be accomplished by quickly shifting out any charge using
a long series of pulses from the V1–V6 outputs. Depending on
the vertical resolution of the CCD, up to 2,000 or 3,000 clock
cycles will be needed to shift the charge out of each vertical CCD
line. This operation will span across multiple HD line lengths.
Normally, the AD9991 vertical timing must be contained within
one HD line length, but when Sweep mode is enabled, the HD
boundaries will be ignored until the region is nished. To enable
Sweep mode within any reg ion, prog ram the appropr iate
SWEEP register to High.
Figure 21 shows an example of the Sweep mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1–V6 output signals are gener-
ated using the V-pattern registers (shown in Table VII). A single
pulse is created using the polarity and toggle position registers.
The number of repetitions is then programmed to match the
number of vertical shifts required by the CCD. Repetitions are
programmed in the V-sequence registers using the VPATREP
registers. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of the
HD line length, but with Sweep mode enabled for this region,
the HD boundaries will be ignored. In Figure 21, the Sweep
region occupies 23 HD lines. After the Sweep mode region is
completed, in the next region, normal sequence operation will
resume. When using Sweep mode, be sure to set the region
boundries (using the sequence change positions) to the appropri-
ate lines to prevent the Sweep operation from overlapping the
next V-sequence.
Multiplier Mode
To generate very wide vertical timing pulses, a vertical region
may be congured into a multiplier region. This mode uses
the V-pattern registers in a slightly different manner. Multiplier
mode can be used to support unusual CCD timing requirements,
such as vertical pulses that are wider than a single HD line length.
The start polarity and toggle positions are still used in the same
manner as the standard VPAT group programming, but the
VPATLEN is used differently. Instead of using the pixel counter
(HD counter) to specify the toggle position locations (VTOG1,
2, 3) of the VPAT group, the VPATLEN is multiplied with the
VTOG position to allow very long pulses to be generated. To cal-
culate the exact toggle position, counted in pixels after the start
position, use the equation
Multiplier Mode Toggle Position = VTOG
VPATLEN
Because the VTOG register is multiplied by VPATLEN,
the resolution of the toggle position placement is reduced. If
VPATLEN = 4, the toggle position accuracy is now reduced
to 4-pixel steps instead of single pixel steps. Table VIII sum-
marizes how the VPAT group registers are used in Multiplier
mode operation. In Multiplier mode, the VPATREPO and
VPATREPE registers should always be programmed to the same
value as the highest toggle position.
VD
V1–V6
HD
REGION 1: SWEEP REGION
LINE 0
LINE 1
REGION 0
REGION 2
LINE 24
LINE 25
LINE 2
SCP 1
SCP 2
Figure 21. Example of Sweep Region for High Speed Vertical Shift
Table VIII. Multiplier Mode Register Parameters
Register
Length
Range
Description
MULTI
1b
High/Low
High enables Multiplier mode.
VPOL
1b
High/Low
Starting Polarity of V1–V6 Signal in Each VPAT Group.
VTOG1
12b
0–4095 Pixel Location
First Toggle Position for V1–V6 Signal in Each VPAT Group.
VTOG2
12b
0–4095 Pixel Location
Second Toggle Position for V1–V6 Signal in Each VPAT Group.
VTOG3
12b
0–4095 Pixel Location
Third Toggle Position for V1–V6 Signal in Each VPAT Group.
VPATLEN
10b
0–1023 Pixels
Used as Multiplier Factor for Toggle Position Counter.
VPATREP
12b
0–4096
VPATREPE/VPATREPO should be set to the same value as TOG2 or 3.
REV. 0
相關PDF資料 |
PDF描述 |
|---|---|
| AD9992BBCZRL | IC CCD SGNL PROC 12BIT 105CSPBGA |
| AD9995KCPZ | IC CCD SIGNAL PROCESSOR 56-LFCSP |
| ADA4424-6ARUZ | IC FILTR VID6CH SD/ED/HD 38TSSOP |
| ADATE302-02BBCZ | IC DCL ATE 500MHZ DUAL 84CSPBGA |
| ADATE304BBCZ | IC DCL ATE 200MHZ DUAL 84CSPBGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9992 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9992BBCZ | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9992BBCZRL | 功能描述:IC CCD SGNL PROC 12BIT 105CSPBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關文件:Automotive Product Guide 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數字 輸出類型:數字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:20-TSSOP 包裝:管件 |
| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復。