參數(shù)資料
型號(hào)： AD9991KCPZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/60頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 2,500
類型： CCD 信號(hào)處理器，10 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9991
–33–
VDD
(INPUT)
SERIAL
WRITES
VD
(OUTPUT)
1 H
1ST FIELD
SYNC
(INPUT)
DIGITAL
OUTPUTS
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER IS UPDATED AT VD/HD EDGE
H1/H3, RG, DCLK
H2/H4
tPWR
CLI
(INPUT)
HD
(OUTPUT)
1V
tSYNC
Figure 35. Recommended Power-Up Sequence and Synchronization, Master Mode
POWER-UP AND SYNCHRONIZATION
Recommended Power-Up Sequence for Master Mode
When the AD9991 is powered up, the following sequence is
recommended (refer to Figure 35 for each step). Note that a
SYNC signal is required for master mode operation. If an exter-
nal SYNC pulse is not available, it is also possible generate an
internal SYNC pulse by writing to the SYNCPOL register, as
described in the next section.
1. Turn on power supplies for AD9991.
2. Apply the master clock input CLI.
3. Reset the internal AD9991 registers by writing a 1 to the
SW_RESET register (addr 0x10 in Bank 1).
4. By default, the AD9991 is in Standby3 mode. To place the
part into normal power operation, write 0x004 to the AFE
OPRMODE register (addr 0x00 in Bank 1).
5. Write a 1 to the BANKSELECT register (addr 0x7F). This
will select Register Bank 2.
6. Load Bank 2 registers with the required VPAT group,
V-sequence, and eld timing information.
7. Write a 0 to the BANKSELECT register to select Bank 1.
8. By default, the internal timing core is held in a reset state with
TGCORE_RSTB register = 0. Write a 1 to the TGCORE_
RSTB register (addr 0x15 in Bank 1) to start the internal
timing core operation.
9. Load the required registers to congure the high speed tim-
ing, horizontal timing, and shutter timing information.
10. Congure the AD9991 for Master mode timing by writing a
1 to the MASTER register (addr 0x20 in Bank 1).
11. Write a 1 to the OUT_CONTROL register (addr 0x11 in
Bank 1). This will allow the outputs to become active after
the next SYNC rising edge.
12. Generate a SYNC event: If SYNC is high at power-up, bring
the SYNC input low for a minimum of 100 ns. Then bring
SYNC back high. This will cause the internal counters to
reset and will start VD/HD operation. The rst VD/HD edge
allows most Bank 1 register updates to occur, including
OUT_CONTROL to enable all outputs.
Table XIII. Power-Up Register Write Sequence
Address
Data
Description
0x10
0x01
Reset All Registers to Default Values
0x00
0x04
Power Up the AFE and CLO Oscillator
0x7F
0x01
Select Register Bank 2
0x00–0xFF
VPAT, V-Sequence, and Field Timing
0x7F
0x00
Select Register Bank 1
0x15
0x01
Reset Internal Timing Core
0x30–71
Horizontal and Shutter Timing
0x20
0x01
Congure for Master Mode
0x11
0x01
Enable All Outputs after SYNC
0x13
0x01
SYNCPOL (for Software SYNC Only)
Generating Software SYNC without External SYNC Signal
If an external SYNC pulse is not available, it is possible to
generate an internal SYNC in the AD9991 by writing to the
SYNCPOL register (addr 0x13). If the software SYNC option is
used, the SYNC input (Pin 46) should be tied to ground (VSS).
After power-up, follow the same procedure as before for Steps
1–11. Then, for Step 12, instead of using the external SYNC
pulse, write a 1 to the SYNCPOL register. This will generate the
SYNC internally, and timing operation will begin.
REV. 0
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