t EXP VSUB MECHANICAL SHUTTER OPEN CLOSED MODE 0 MODE 1 MSHUT STR OBE SERIAL WRITES" />
參數(shù)資料
型號： AD9991KCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 24/60頁
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROCESSOR 56-LFCSP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標準包裝： 2,500
類型： CCD 信號處理器，10 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應商設備封裝： 56-LFCSP-VQ（8x8）
包裝： 帶卷 (TR)
AD9991
–30–
VD
SUBCK
t EXP
VSUB
MECHANICAL
SHUTTER
OPEN
CLOSED
MODE
0
MODE
1
MSHUT
STR
OBE
SERIAL
WRITES
OPEN
VSG
STILL
IMA
GE
READOUT
CCD
OUT
DRAFT
IMAGE
STILL
IMAGE
1ST
FIELD
STILL
IMAGE
2ND
FIELD
STILL
IMAGE
3RD
FIELD
DRAFT
IMAGE
DRAFT
IMAGE
Figure
32.
Example
of
Exposure
and
Still
Image
R
eadout
Using
Shut
ter
Signals
and
Mode
R
egister
1.
Wr
ite
to
the
READOUT
reg
ister
(addr
0x61)
to
specify
the
number
of
elds
to
fur
ther
suppress
SUBCK
while
the
CCD
da
ta
is
read
out.
In
this
example,
READOUT
=
3.
Write
to
the
EXPOSURE
register
(addr
0x62)
to
specify
the
number
of
elds
to
suppress
SUBCK
and
VSG
outputs
during
exposure.
In
this
example,
EXPOSURE
=
1.
Wr
ite
to
the
TRIGGER
reg
ister
(addr
0x60)
to
enable
the
STR
OBE,
MSHUT
,
and
VSUB
signals,
and
to
star
tthe
exposure/readout
opera
tion.
T
o
tr
igger
all
of
these
ev
ents
(as
in
Figure
32),
set
the
reg
ister
TRIGGER
=
31.
Readout
will
automa
tically
occur
after
the
exposure
per
iod
is
nished.
Wr
ite
to
the
MODE
reg
ister
(0x1B)
to
con
gure
the
next
ve
elds
.The
r
st
tw
o
elds
dur
ing
exposure
are
the
same
as
the
cur
rent
draft
mode
elds,
and
the
follo
wing
three
elds
are
the
still
frame
readout
elds
.The
reg
ister
sfor
the
Draft
mode
eld
and
the
three
readout
elds
ha
ve
already
been
prog
rammed.
2.
VD/HD
f
alling
edge
will
upda
te
the
ser
ial
wr
ites
from
1.
3.
If
VSUB
mode
=
0
(addr
0x67),
VSUB
output
tur
ns
on
a
tthe
line
speci
ed
in
the
VSUBON
reg
ister
(addr
0x68).
4.
STR
OBE
output
tur
ns
on
and
off
a
tthe
loca
tion
speci
ed
in
the
STR
OBEON
and
OFF
reg
ister
s(addr
0x6E
to
0x71).
5.
MSHUT
output
tur
ns
off
a
tthe
loca
tion
speci
ed
in
the
MSHUT
OFF
reg
is-
ter
s(addr
0x6B
and
0x6C).
6.
The
next
VD
f
alling
edge
will
automa
tically
star
tthe
rst
readout
eld.
7.
The
next
VD
f
alling
edge
will
automa
tically
star
tthe
second
readout
eld.
8.
The
next
VD
f
alling
edge
will
automa
tically
star
tthe
third
readout
eld.
9.
Wr
ite
to
the
MODE
reg
ister
to
recon
gure
the
single
Draft
mode
eld
timing.
Wr
ite
to
the
MSHUT
ON
reg
ister
(addr
0x6A)
to
open
the
mechanical
shutter
.
10.
VD/HD
f
alling
edge
will
upda
te
the
ser
ial
wr
ites
from
9.
VSG
outputs
retur
n
to
Draft
mode
timing.
SUBCK
output
resumes
opera
tion.
MSHUT
output
retur
ns
to
the
on
position
(activ
eor
open).
VSUB
output
retur
ns
to
the
off
position
(inactiv
e).
REV. 0
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