參數(shù)資料
型號： AD9974BBCZRL
廠商： Analog Devices Inc
文件頁數(shù)： 43/52頁
文件大小： 0K
描述： IC CCDSP DUAL 14BIT 100-CSPBGA
標準包裝： 1
類型： CCD 信號處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 55mA
安裝類型： 表面貼裝
封裝/外殼： 100-LFBGA，CSPBGA
供應商設備封裝： 100-CSBGA（9x9）
包裝： 標準包裝
其它名稱： AD9974BBCZRLDKR
AD9974
Rev. A | Page 48 of 52
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x05
[12:0]
X
SCP
HBLKTOGE5
Fifth HBLK Toggle Position for Even Lines, or RA4H2REPA/B/C.
[25:13]
X
HBLKTOGE6
Sixth HBLK Toggle Position for Even Lines, or RA5H2REPA/B/C.
[27:26]
X
Unused
Set unused bits to 0.
0x06
[12:0]
X
SCP
HBLKSTARTA
HBLK Repeat Area Start Position A. Used during HBLK Mode 2.
[25:13]
X
HBLKSTARTB
HBLK Repeat Area Start Position B. Used during HBLK Mode 2.
[27:26]
X
Unused
Set unused bits to 0.
0x07
[12:0]
X
SCP
HBLKSTARTC
HBLK Repeat Area Start Position C. Used during HBLK Mode 2.
[27:13]
X
Unused
Set unused bits to 0.
0x08
[2:0]
X
SCP
HBLKALT_PAT1
HBLK Pattern 1 Order. Used during pixel mixing mode.
[5:3]
X
HBLKALT_PAT2
HBLK Pattern 2 Order. Used during pixel mixing mode.
[8:6]
X
HBLKALT_PAT3
HBLK Pattern 3 Order. Used during pixel mixing mode.
[11:9]
X
HBLKALT_PAT4
HBLK Pattern 4 Order. Used during pixel mixing mode.
[14:12]
X
HBLKALT_PAT5
HBLK Pattern 5 Order. Used during pixel mixing mode.
[17:15]
X
HBLKALT_PAT6
HBLK Pattern 6 Order. Used during pixel mixing mode.
[19:18]
X
HBLK_MODE
HBLK Mode Selection.
0 = normal HBLK.
1 = pixel mixing mode.
2 = special pixel mixing mode.
3 = not used.
[20]
X
TESTMODE
Test Operation Only. Set to 0.
[27:21]
X
Unused
Set unused bits to 0.
0x09
[12:0]
X
SCP
HBLKLEN
HBLK Length in HBLK Alteration Modes.
[20:13]
X
HBLKREP
Number of HBLK Repetitions in HBLK Alternation Modes.
[21]
X
HBLKMASK_H1
Masking Polarity for H1/H3 During HBLK.
[22]
X
HBLKMASK_H2
Masking Polarity for H2/H4 During HBLK.
[27:23]
X
Unused
Set unused bits to 0.
0xA
[12:0]
X
SCP
HBLKSTART
HBLK Start Position Used in Pixel Mixing Modes.
[25:13]
X
HBLKEND
HBLK End Position Used in Pixel Mixing Modes.
[27:26]
X
Unused
Set unused bits to 0.
0xB
[27:0]
X
SCP
TESTMODE
Test Operation Only. Set to 0.
0xC
[12:0]
X
SCP
CLPOB0_TOG1
CLPOB0 Toggle Position 1.
[25:13]
X
CLPOB0_TOG2
CLPOB0 Toggle Position 2.
[27:26]
X
Unused
Set unused bits to 0.
0xD
[12:0]
X
SCP
CLPOB1_TOG1
CLPOB1 Toggle Position 1.
[25:13]
X
CLPOB1_TOG2
CLPOB1 Toggle Position 2.
[27:26]
X
Unused
Set unused bits to 0.
0xE
[12:0]
X
SCP
PBLK0_TOG1
PBLK0 Toggle Position 1.
[25:13]
X
PBLK0_TOG2
PBLK0 Toggle Position 2.
[27:26]
X
Unused
Set unused bits to 0.
0xF
[12:0]
X
SCP
PBLK1_TOG1
PBLK1 Toggle Position 1.
[25:13]
X
PBLK1_TOG2
PBLK1 Toggle Position 2.
[27:26]
X
Unused
Set unused bits to 0.
Table 31. Field Registers
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x00
[12:0]
X
VD
SCP0
Sequence Change Position 0.
[25:13]
X
SCP1
Sequence Change Position 1.
[27:26]
X
Unused
Set unused bits to 0.
0x01
[12:0]
X
VD
SCP2
Sequence Change Position 2.
[25:13]
X
SCP3
Sequence Change Position 3.
[27:26]
X
Unused
Set unused bits to 0.
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