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| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 37/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 42 of 52
COMPLETE REGISTER LISTING
All addresses and default values are expressed in hexadecimal. When an address contains less than 28 data bits, all remaining bits must be
written as 0s. All TESTMODE registers must be set to the specified values.
Table 22. AFE Registers
Address
Data Bit
Content
Default
Value
Update
Name
Description
0x00
[1:0]
3
SCK
STANDBY
Standby Modes.
0 = normal operation.
1= band gap reference in standby.
2, 3 = total power-down.
[2]
1
REFBUF_PWRDN
Reference Buffer for REFT and REFB Power Control.
0 = REFT/REFB internally driven.
1 = REFT/REFB not driven.
[3]
1
CLAMPENABLE
Clamp Enable Control.
0 = disable black clamp.
1 = enable black clamp.
[5:4]
0
TESTMODE
Test Operation Only. Set to 0.
[6]
0
PBLK_LVL
PBLK Level Control.
0 = blank to 0.
1 = blank to clamp level.
[7]
0
DCBYP
DC Restore Circuit Control.
0 = enable dc restore circuit during PBLK.
1 = bypass dc restore circuit during PBLK.
[9:8]
0
CDSMODE
CDS Operation.
0 = normal (inverting) CDS mode.
1 = sample and hold (SHA) mode.
2 = positive CDS mode.
3 = invalid, do not use.
[16:10]
0
TESTMODE
Test Operation Only. Set to 0.
[27:17]
Unused
Set unused bits to 0.
0x01
[1:0]
0
SCK
TESTMODE
Test Operation Only. Set to 0.
[2]
0
GRAYENCODE
Gray Coding ADC Outputs.
0 = disable.
1 = enable.
[3]
0
TESTMODE
Test Operation Only. Set to 0.
[4]
1
TESTMODE
Test Operation Only. Set to 0.
[27:5]
Unused
Set unused bits to 0.
0x02
[0]
0
SCK
TESTMODE
Test Operation Only. Set to 0.
[27:1]
Unused
Set unused bits to 0.
0x03
[23:0]
FFFFFF
SCK
TESTMODE
Test Operation Only. Set to FFFFFF.
[27:24]
Unused
Set unused bits to 0.
0x04
[1:0]
1
VD
CDSGAIN
CDS Gain Setting.
0 = 3 dB.
1 = 0 dB (default).
2 = +3 dB.
3 = +6 dB.
[27:2]
Unused
Set unused bits to 0.
0x05
[9:0]
F
VD
VGAGAIN
VGA Gain. 6 dB to 42 dB (0.035 dB per step).
[27:10]
Unused
Set unused bits to 0.
0x06
[9:0]
1EC
VD
CLAMPLEVEL
Optical Black Clamp Level. 0 LSB to 1023 LSB (1 LSB per step).
[27:10]
Unused
Set unused registers to 0.
0x07
[27:0]
0
TESTMODE
Test Operation Only. Set to 0 if this register is accessed.
0x08
[27:0]
0
TESTMODE
Test Operation Only. Set to 0 if this register is accessed.
0x09
[27:0]
0
TESTMODE
Test Operation Only. Set to 0 if this register is accessed.
0x0A
[27:0]
0
TESTMODE
Test Operation Only. Set to 0 if this register is accessed.
0x0B
[27:0]
0
TESTMODE
Test Operation Only. Set to 0 if this register is accessed.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
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