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| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 28 of 52
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 36 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels that occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two
at the back of the readout. The horizontal direction has four
OB pixels in the front and 48 in the back.
Figure 37 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
Because PBLK is used to isolate the CDS input (see the Analog
Front End Description and Operation section), do not use the
PBLK signal during CLPOB operation. The change in the offset
behavior that occurs during PBLK impacts the accuracy of the
CLPOB circuitry.
The HBLK, CLPOB, and PBLK parameters are programmed
in the V-sequence registers. More elaborate clamping schemes,
such as adding a separate sequence to clamp all the shielded
OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.
The CLPOBMASK registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
clamping sequences. It is important to use CLPOB only during
valid OB pixels. During other portions on the frame timing,
such as vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulse that occurs during
this time causes errors in clamping operation and, therefore,
changes in the black level of the image.
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL
OB LINES
2 VERTICAL
OB LINES
V
H
05
95
5-
0
36
Figure 36. Example CCD Configuration
VERTICAL SHIFT
VERT. SHIFT
CCD OUTPUT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
OPTICAL BLACK
DUMMY
EFFECTIVE PIXELS
OB
OPTICAL BLACK
HD
NOTES
1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).
0
59
55
-0
37
Figure 37. Horizontal Sequence Example
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