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參數(shù)資料
| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標準包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應商設備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標準包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
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AD9974
Rev. A | Page 33 of 52
APPLICATIONS INFORMATION
RECOMMENDED POWER-UP SEQUENCE
When the AD9974 is powered up, the following sequence is
recommended (see Figure 48 for each step).
1.
Turn on the power supplies for the AD9974 and apply CLI
clock. There is no required sequence for turning on each
supply.
2.
Although the AD9974 contains an on-chip power-on reset,
a software reset of the internal registers is recommended.
Write 1 to the SW_RST register (Address 0x10) to reset all
the internal registers to their default values. This bit is self-
clearing and automatically resets to 0.
3.
Write to the desired registers to configure high speed timing
and horizontal timing. Note that all TESTMODE registers
must be written as described in the Complete Register
Listing section.
4.
To place the part into normal power operation, write 0 to the
STANDBY and REFBUF_PWRDN registers (Address 0x00).
5.
The Precision Timing core must be reset by writing 1 to the
TGCORE_RST register (Address 0x14). This starts the
internal timing core operation.
6.
Write 1 to the OUT_CONTROL register (Address 0x11).
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL, which enables all clock outputs.
Additional Restrictions
When operating, note the following restrictions:
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or after the VD falling
edge. The HD falling edge should not be located between
one and five cycles prior to the VD falling edge.
If possible, perform all start-up serial writes with VD and
HD disabled. This prevents unknown behavior caused by
partial updating of registers before all information is loaded.
The internal horizontal counter is reset 12 CLI cycles after the
falling edge of HD. See Figure 49 for details on how the internal
counter is reset.
POWER
SUPPLIES
CLI
(INPUT)
SERIAL
WRITES
VD
(INPUT)
HD
(INPUT)
HI-Z BY
DEFAULT
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE
1H
1ST FIELD
1V
0V
AD9974 SUPPLIES
H-CLOCKS
H1, H3, RG
H2, H4
4
23
5
6
1
05
9
5
5-
04
8
Figure 48. Recommended Power-Up Sequence
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相關代理商/技術參數(shù) |
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|---|---|
| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END WITH HALF DUPLEX - Tape and Reel |
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