- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1895 > AD9974BBCZRL (Analog Devices Inc)IC CCDSP DUAL 14BIT 100-CSPBGA PDF資料下載
參數(shù)資料
| 型號： | AD9974BBCZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCDSP DUAL 14BIT 100-CSPBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | CCD 信號處理器，14 位 |
| 輸入類型： | 邏輯 |
| 輸出類型： | 邏輯 |
| 接口： | 3 線串口 |
| 電流 - 電源： | 55mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LFBGA，CSPBGA |
| 供應(yīng)商設(shè)備封裝： | 100-CSBGA（9x9） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD9974BBCZRLDKR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁當(dāng)前第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁
AD9974
Rev. A | Page 41 of 52
UPDATING OF REGISTER VALUES
The internal registers of the AD9974 are updated at different
times, depending on the particular register.
Table 21 summarizes the three types of register updates. The
tables in the Complete Register Listing section also contain a
column with update type to identify when each register is updated.
SCK Updated—Some of the registers are updated immediately
as the 28th data bit (D27) is written. These registers are
used for functions that do not require gating with the next
VD boundary, such as power-up and reset functions.
VD Updated—Many of the registers are updated at the
next VD falling edge. By updating these values at the next
VD edge, the current field is not corrupted, and the new
register values are applied to the next field. The VD update
can be further delayed past the VD falling edge by using
UPDATE Register Address 0x17. This delays the VD-updated
register updates to any HD line in the field. Note that the
field registers are not affected by the UPDATE register.
SCP Updated—All of the H-pattern group registers are
updated at the next SCP when they are used.
Table 21. Register Update Types
Update Type
Description
SCK Updated
Register is immediately updated when the 28th data bit (D27) is clocked in.
VD Updated
Register is updated at the VD falling edge. VD-updated registers can be delayed further by using the UPDATE register at
Address 0x17. Field registers are not affected by the UPDATE register.
SCP Updated
Register is updated at the next SCP when the register is used.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9979BCPZRL | IC PROCESSOR CCD 14BIT 48-LFCSP |
| AD9980KSTZ-95 | IC INTERFACE 8BIT ANALOG 80LQFP |
| AD9981KSTZ-95 | IC INTERFACE 10BIT ANALOG 80LQFP |
| AD9983AKSTZ-170 | IC DISPLAY 8BIT 170MSPS 80LQFP |
| AD9985KSTZ-140 | IC INTERFACE 8BIT 140MSPS 80LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9975 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABST | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTEB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975ABSTRL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed-Signal Front End |
| AD9975BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:10 BIT ANALOG FRONT END WITH HALF DUPLEX - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。