參數(shù)資料
型號(hào): AD9958BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 42/44頁
文件大小: 0K
描述: IC DDS DUAL 500MSPS DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝: 1
分辨率(位): 10 b
主 fclk: 500MHz
調(diào)節(jié)字寬(位): 32 b
電源電壓: 1.71 V ~ 1.96 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
產(chǎn)品目錄頁面: 552 (CN2011-ZH PDF)
配用: AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958
Data Sheet
AD9958
Rev. B | Page 7 of 44
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Total Power Dissipation—Both Channels On, Single-
Tone Mode
315
380
mW
Dominated by supply variation
Total Power Dissipation—Both Channels On, with
Sweep Accumulator
350
420
mW
Dominated by supply variation
Total Power Dissipation—Full Power-Down
13
mW
IAVDD—Both Channels On, Single-Tone Mode
90
105
mA
IAVDD—Both Channels On, Sweep Accumulator,
REFCLK Multiplier, and 10-Bit Output Scalar
Enabled
95
110
mA
IDVDD—Both Channels On, Single-Tone Mode
60
70
mA
IDVDD—Both Channels On, Sweep Accumulator,
REFCLK Multiplier, and 10-Bit Output Scalar
Enabled
70
80
mA
IDVDD_I/O
22
mA
IDVDD = read
30
mA
IDVDD = write
IAVDD Power-Down Mode
2.5
mA
IDVDD Power-Down Mode
2.5
mA
DATA LATENCY (PIPELINE DELAY) SINGLE-TONE MODE2, 3
Frequency, Phase, and Amplitude Words to DAC
Output with Matched Latency Enabled
29
SYSCLKs
Frequency Word to DAC Output with Matched
Latency Disabled
29
SYSCLKs
Phase Offset Word to DAC Output with Matched
Latency Disabled
25
SYSCLKs
Amplitude Word to DAC Output with Matched
Latency Disabled
17
SYSCLKs
DATA LATENCY (PIPELINE DELAY) MODULATION MODE3, 4
Frequency Word to DAC Output
34
SYSCLKs
Phase Offset Word to DAC Output
29
SYSCLKs
Amplitude Word to DAC Output
21
SYSCLKs
DATA LATENCY (PIPELINE DELAY) LINEAR SWEEP MODE3,4
Frequency Rising/Falling Delta-Tuning Word to DAC
Output
41
SYSCLKs
Phase Offset Rising/Falling Delta-Tuning Word to
DAC Output
37
SYSCLKs
Amplitude Rising/Falling Delta-Tuning Word to DAC
Output
29
SYSCLKs
1
For the VCO frequency range of 160 MHz to 255 MHz, there is no guarantee of operation.
2
Data latency is referenced to I/O_UPDATE.
3
Data latency is fixed.
4
Data latency is referenced to a profile change.
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