參數(shù)資料
型號(hào)： AD9958BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 35/44頁(yè)
文件大?。?/td> 0K
描述： IC DDS DUAL 500MSPS DAC 56LFCSP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
Phase Coherent FSK Modulator (CN0186)
標(biāo)準(zhǔn)包裝： 1
分辨率（位）： 10 b
主 fclk： 500MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 1.71 V ~ 1.96 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 56-LFCSP-VQ（8x8）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
配用： AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958
AD9958
Data Sheet
Rev. B | Page 40 of 44
Bit
Mnemonic
Description
6
External power-down mode
0 = the external power-down mode is in fast recovery power-down mode (default). In this mode,
when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are not powered
down.
1 = the external power-down mode is in full power-down mode. In this mode, when the
PWR_DWN_CTL input pin is high, all functions are powered down. This includes the DAC and PLL,
which take a significant amount of time to power up.
5
SYNC_CLK disable
0 = the SYNC_CLK pin is active (default).
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive logic is
shut down. However, the synchronization circuitry remains active internally to maintain normal
device operation.
4
DAC reference power-down
0 = DAC reference is enabled (default).
1 = DAC reference is powered down.
3:2
Open
1
Manual hardware sync
0 = the manual hardware synchronization feature of multiple devices is inactive (default).
1 = the manual hardware synchronization feature of multiple devices is active.
0
Manual software sync
0 = the manual software synchronization feature of multiple devices is inactive (default).
1 = the manual software synchronization feature of multiple devices is active. See the
Function Register 2 (FR2)—Address 0x02
Two bytes are assigned to this register. The FR2 is used to control the various functions, features, and modes of the AD9958.
Table 33. Bit Descriptions for FR2
Bit
Mnemonic
Description
15
All channels autoclear sweep
accumulator
0 = a new delta word is applied to the input, as in normal operation, but not loaded into the
accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the sweep accumulator for one
cycle upon reception of the I/O_UPDATE sequence indicator on both channels.
14
All channels clear
0 = the sweep accumulator functions as normal (default).
sweep accumulator
1 = the sweep accumulator memory elements for both channels are asynchronously cleared.
13
All channels autoclear phase
accumulator
0 = a new frequency tuning word is applied to the inputs of the phase accumulator, but not
loaded into the accumulator (default).
1 = this bit automatically and synchronously clears (loads 0s into) the phase accumulator for one
cycle upon receipt of the I/O update sequence indicator on both channels.
12
All channels clear phase
0 = the phase accumulator functions as normal (default).
Accumulator
1 = the phase accumulator memory elements for both channels are asynchronously cleared.
11:8
Open
7
Auto sync enable
See the Synchronizing Multiple AD9958 Devices section for more details.
6
Multidevice sync master enable
See the Synchronizing Multiple AD9958 Devices section for more details.
5
Multidevice sync status
See the Synchronizing Multiple AD9958 Devices section for more details.
4
Multidevice sync mask
See the Synchronizing Multiple AD9958 Devices section for more details.
3: 2
Open
1:0
System clock offset
See the Synchronizing Multiple AD9958 Devices section for more details.
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