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參數(shù)資料
| 型號： | AD9958BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS DUAL 500MSPS DAC 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計資源： | Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186) |
| 標準包裝： | 1 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調(diào)節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 552 (CN2011-ZH PDF) |
| 配用： | AD9958/PCBZ-ND - BOARD EVALUATION FOR AD9958 |
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Data Sheet
AD9958
Rev. B | Page 41 of 44
DESCRIPTIONS FOR CHANNEL REGISTERS
Channel Function Register (CFR)—Address 0x03
Three bytes are assigned to this register.
Table 34. Bit Descriptions for CFR
Bit
Mnemonic
Description
23:22
Amplitude frequency
phase (AFP) select
Controls what type of modulation is to be performed for that channel. See the Modulation Mode section
for details.
21:16
Open
15
Linear sweep no-dwell
0 = the linear sweep no-dwell function is inactive (default).
1 = the linear sweep no-dwell function is active. If CFR[15] is active, the linear sweep no-dwell function is
activated. See the Linear Sweep Mode section for details. If CFR[14] is clear, this bit is don’t care.
14
Linear sweep enable
0 = the linear sweep capability is inactive (default).
1 = the linear sweep capability is enabled. When enabled, the delta frequency tuning word is applied to
the frequency accumulator at the programmed ramp rate.
13
Load SRR at
I/O_UPDATE
0 = the linear sweep ramp rate timer is loaded only upon timeout (timer = 1) and is not loaded because
of an I/O_UPDATE input signal (default).
1 = the linear sweep ramp rate timer is loaded upon timeout (timer = 1) or at the time of an I/O_UPDATE
input signal.
12:11
Open
10
Must be 0
Must be set to 0.
9:8
DAC full-scale current
control
11 = the DAC is at the largest LSB value (default).
See Table 5 for other settings.
7
Digital power-down
0 = the digital core is enabled for operation (default).
1 = the digital core is disabled and is in its lowest power dissipation state.
6
DAC power-down
0 = the DAC is enabled for operation (default).
1 = the DAC is disabled and is in its lowest power dissipation state.
5
Matched pipe delays
0 = matched pipe delay mode is inactive (default).
active
1 = matched pipe delay mode is active. See the Single-Tone Mode—Matched Pipeline Delay section for
details.
4
Autoclear sweep
accumulator
0 = the current state of the sweep accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = the sweep accumulator is automatically and synchronously cleared for one cycle upon receipt of an
I/O_UPDATE signal.
3
Clear sweep
0 = the sweep accumulator functions as normal (default).
accumulator
1 = the sweep accumulator memory elements are asynchronously cleared.
2
Autoclear phase
accumulator
0 = the current state of the phase accumulator is not impacted by receipt of an I/O_UPDATE signal
(default).
1 = the phase accumulator is automatically and synchronously cleared for one cycle upon receipt of an
I/O_UPDATE signal.
1
Clear phase
0 = the phase accumulator functions as normal (default).
accumulator
1 = the phase accumulator memory elements are asynchronously cleared.
0
Sine wave output
0 = the angle-to-amplitude conversion logic employs a cosine function (default).
enable
1 = the angle-to-amplitude conversion logic employs a sine function.
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| AD9958BCPZ-REEL7 | 功能描述:IC DDS DUAL 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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